[all-commits] [llvm/llvm-project] 33e5d0: [CostModel][X86] merge vector shuffle costs tests ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 33e5d013b7f7a6ae136a058f842b30c87623ecfb
      https://github.com/llvm/llvm-project/commit/33e5d013b7f7a6ae136a058f842b30c87623ecfb
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-03-18 (Tue, 18 Mar 2025)

  Changed paths:
    R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-load-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-load-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-load-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-load.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-replication-i16.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-replication-i32.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-replication-i64.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-replication-i8.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-reverse-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-reverse-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-reverse-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-reverse.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-select-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-select-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-select-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-select.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-single-src-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-single-src-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-single-src-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-single-src.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-splat-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-splat-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-splat-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-splice-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-splice-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-splice-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-splice.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-transpose-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-transpose-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-transpose-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
    R llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll

  Log Message:
  -----------
  [CostModel][X86] merge vector shuffle costs tests using -cost-kind=all (#131819)



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