[all-commits] [llvm/llvm-project] 8ffda9: [RISCV] Update MicroOpBufferSize in P400 & P600 sc...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ffda96dbedeeaf8c000ec7ee2a156d1d6e3fd2a
      https://github.com/llvm/llvm-project/commit/8ffda96dbedeeaf8c000ec7ee2a156d1d6e3fd2a
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s

  Log Message:
  -----------
  [RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (#128786)

The numbers we previously picked for MicroOpBufferSize in both P400 and
P600's scheduling models turned out to be too conservative and didn't
properly reflect the characteristics of our microarchitectures. This
patch updates these numbers to be more faithful to our hardware.

This is unlikely to have any significant impact on MachineScheduler as
it only uses MicroOpBufferSize in few places. That said, it is supposed
to improve the accuracy of llvm-mca.



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