[all-commits] [llvm/llvm-project] 28cf32: [LLVM] Port a few InstCombine tests to use splat i...

Wed Feb 26 03:14:54 PST 2025

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 28cf323e8717cd57984b5d5b0d7c90cbce0fc54f
      https://github.com/llvm/llvm-project/commit/28cf323e8717cd57984b5d5b0d7c90cbce0fc54f
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/test/Transforms/InstCombine/scalable-const-fp-splat.ll
    M llvm/test/Transforms/InstCombine/scalable-select.ll
    M llvm/test/Transforms/InstCombine/select-masked_gather.ll
    M llvm/test/Transforms/InstCombine/udiv-pow2-vscale.ll
    M llvm/test/Transforms/InstCombine/vector_gep1.ll
    M llvm/test/Transforms/InstSimplify/ConstProp/extractelement-vscale.ll

  Log Message:
  -----------
  [LLVM] Port a few InstCombine tests to use splat instead of shufflevector.

  Commit: 575656877f1f42a4996a551caa7a2c9145810813
      https://github.com/llvm/llvm-project/commit/575656877f1f42a4996a551caa7a2c9145810813
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    R llvm/test/Transforms/InstCombine/AArch64/sve-inst-combine-cmpne.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul-idempotency.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul_u-idempotency.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-idempotency.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul_u-idempotency.ll
    M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll

  Log Message:
  -----------
  [LLVM][AArch64] Reduce uses of "undef" in SVE InstCombine tests.

Also removes a largely duplicate test file and changes the other
one to use autogenerated CHECK lines.

  Commit: 6f2345a20e361c7748578b0c3bae37589989e3b8
      https://github.com/llvm/llvm-project/commit/6f2345a20e361c7748578b0c3bae37589989e3b8
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/test/CodeGen/AArch64/pr49781.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-gep.ll
    M llvm/test/CodeGen/AArch64/sve-int-log.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
    M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-vselect-imm.ll

  Log Message:
  -----------
  [LLVM][AArch64] Change SVE CodeGen tests to use splat().

The affected tests were using the longwinded syntax for constant
splats. By using the splat() syntax the tests get simplified whilst
also removing the need for "undef".

  Commit: 01371d64a91ed65d18670a1ee570058a0678ce0b
      https://github.com/llvm/llvm-project/commit/01371d64a91ed65d18670a1ee570058a0678ce0b
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
    M llvm/test/CodeGen/AArch64/aarch64-sve-and-combine-crash.ll
    M llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
    M llvm/test/CodeGen/AArch64/sub-splat-sub.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
    M llvm/test/CodeGen/AArch64/sve-extract-element.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
    M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
    M llvm/test/CodeGen/AArch64/sve-insert-element.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
    M llvm/test/CodeGen/AArch64/sve-ld1r.ll
    M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-scaled.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-unscaled.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-scaled.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-unscaled.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-scaled.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-unscaled.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-imm.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-reg.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
    M llvm/test/CodeGen/AArch64/sve-split-load.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-unary-movprfx.ll
    M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
    M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
    M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
    M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-unary-movprfx.ll
    M llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll

  Log Message:
  -----------
  [LLVM][AArch64] Reduce uses of "undef" in SVE CodeGen tests.

Using "poison" better reflects realworld generated IR. The main idioms
ported are:
* Inserting into an undefined vector.
* Vector splats.
* Masked load/gather operations with an undefined passthrough.

Compare: https://github.com/llvm/llvm-project/compare/0ba2000b3cec...01371d64a91e

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