[all-commits] [llvm/llvm-project] 1937a3: [RISCV] Add @earlyclobber to SiFive custom matrix ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1937a36209bc5f3636e7c98a1638ee9f082b4d2b
      https://github.com/llvm/llvm-project/commit/1937a36209bc5f3636e7c98a1638ee9f082b4d2b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-23 (Thu, 23 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

  Log Message:
  -----------
  [RISCV] Add @earlyclobber to SiFive custom matrix multiply instruction. (#124060)

All of these have a constraint that vd and vs1 cannot overlap. Some of
them have an additional widening constraint for vs2. We should use
earlyclobber to protect this.

This is unlikely to be an issue in practice due to the instrinsic being
ternary so vd is also a source. The intrinsic has a different type for
this source than the other sources. You would have to do something crazy
to get the register allocator to overlap the registers.



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