[all-commits] [llvm/llvm-project] 4bd044: [RISCV] Add RVVConstraint to SiFive custom matrix ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4bd0440bd2a653644987dddf8ec8d9d1f258ce31
      https://github.com/llvm/llvm-project/commit/4bd0440bd2a653644987dddf8ec8d9d1f258ce31
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-23 (Thu, 23 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    A llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s
    A llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s

  Log Message:
  -----------
  [RISCV] Add RVVConstraint to SiFive custom matrix multiply instructions. (#124055)

The instructions don't allow the vs1 encoded register to overlap vd.
Confusingly these instructions order their operands vd, vs1, vs2 while
every other vector instruction is vd, vs2, vs1. So we need to use
VS2Constraint for this since it checks the first operand after vd.

2 of the 3 extensions have instruction that produce a result with
EMUL=2*LMUL. This makes them subject to the widening constraints for
vs2. So for these extensions we use WidenV which includes VS2Constraint.



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