[all-commits] [llvm/llvm-project] 09583d: AMDGPU: Reduce 64-bit add width if low bits are kn...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 09583dec15c5100fd5f26f81a1b011bce3f9b21f
      https://github.com/llvm/llvm-project/commit/09583dec15c5100fd5f26f81a1b011bce3f9b21f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-01-08 (Wed, 08 Jan 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll

  Log Message:
  -----------
  AMDGPU: Reduce 64-bit add width if low bits are known 0 (#122049)

If one of the inputs has all 0 bits, the low part cannot
carry and we can just pass through the original value.

Add case: https://alive2.llvm.org/ce/z/TNc7hf
Sub case: https://alive2.llvm.org/ce/z/AjH2-J

We could do this in the general case with computeKnownBits,
but add is so common this could be potentially expensive for
something which will fire infrequently.

One potential concern is this could break the 64-bit add
we expect to see for addressing mode matching, but these
constants shouldn't appear often in addressing expressions.
One test for large offset expressions changes but isn't worse.

Fixes https://github.com/ROCm/llvm-project/issues/237



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications