[all-commits] [llvm/llvm-project] 9d0fa4: [mlir] Update Ch-2.md (#121379)
Fangrui Song via All-commits
all-commits at lists.llvm.org
Mon Jan 6 20:09:39 PST 2025
Branch: refs/heads/users/MaskRay/spr/lld-machobalancedpartition-simplify-relocation-hash-and-avoid-xxhash
Home: https://github.com/llvm/llvm-project
Commit: 9d0fa42fbbffe3ff584b26f3a48f8f786f68da72
https://github.com/llvm/llvm-project/commit/9d0fa42fbbffe3ff584b26f3a48f8f786f68da72
Author: Vishakh Prakash <vishakhpro2002 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M mlir/docs/Tutorials/Toy/Ch-2.md
Log Message:
-----------
[mlir] Update Ch-2.md (#121379)
line 265 in the file llvm-project/mlir/docs/Tutorials/Toy/Ch-2.md
changed mlir::OpTraits to mlir::OpTrait
Commit: 510263a969291749ba2b627839249b2bb101ca35
https://github.com/llvm/llvm-project/commit/510263a969291749ba2b627839249b2bb101ca35
Author: Nico Weber <thakis at chromium.org>
Date: 2025-01-05 (Sun, 05 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
Log Message:
-----------
[gn] port a774adb01725 (BuiltinsX86_64.td)
Commit: f3590c16da9e6bb5c3b22f4593ef794a43dc8b5d
https://github.com/llvm/llvm-project/commit/f3590c16da9e6bb5c3b22f4593ef794a43dc8b5d
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-01-05 (Sun, 05 Jan 2025)
Changed paths:
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.rst
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
Log Message:
-----------
[Clang][ASTMatcher] Add a matcher for the name of a DependentScopeDeclRefExpr (#121656)
Add the `hasDependentName` matcher to match the name of
`DependentScopeDeclRefExpr`
Fixes https://github.com/llvm/llvm-project/issues/121610
Commit: d34f7ead886aaaca50f672c47e4f97e078d574db
https://github.com/llvm/llvm-project/commit/d34f7ead886aaaca50f672c47e4f97e078d574db
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
Log Message:
-----------
DAG: Fix assuming f16 is the only 16-bit fp type in concat vector combine (#121637)
This would see if there are mixed integer and FP types and pick an
equivalently sized FP type to use as the vector element type, and only
cast if there were mixed integers. We need to insert a cast if the types
are mixed, which may include different FP types.
Fixes #121601
Commit: 0bd1c879966cfdf145b1f96292a2632628fab3fb
https://github.com/llvm/llvm-project/commit/0bd1c879966cfdf145b1f96292a2632628fab3fb
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
R llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
Log Message:
-----------
[AMDGPU] Support divergent sized dynamic alloca (#121148)
Currently, AMDGPU backend can handle uniform-sized dynamic allocas.
This patch extends support for divergent-sized dynamic allocas.
When the size argument of a dynamic alloca is divergent,
a wave-wide reduction is performed to get the required stack space.
`@llvm.amdgcn.wave.reduce.umax` is used to perform the
wave reduction.
Dynamic allocas are not completely supported yet,
as the stack is not properly restored on function exit.
This patch doesn't attempt to address the aforementioned issue.
Note: Compiler already Zero-Extends or Truncates all other
types(of alloca size arg) to i32.
Commit: 7e3180a2c2ca2383688d4b8a74c99ce486dd8486
https://github.com/llvm/llvm-project/commit/7e3180a2c2ca2383688d4b8a74c99ce486dd8486
Author: Amara Emerson <amara at apple.com>
Date: 2025-01-05 (Sun, 05 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
Log Message:
-----------
[AArch64][GlobalISel] Add support for widening vector store elements to s8.
Reviewers: topperc, arsenm, davemgreen
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/121170
Commit: 41ebbed280e9e4e8fa3b394486fad70d1af4c797
https://github.com/llvm/llvm-project/commit/41ebbed280e9e4e8fa3b394486fad70d1af4c797
Author: Amara Emerson <amara at apple.com>
Date: 2025-01-05 (Sun, 05 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
Log Message:
-----------
[AArch64][GlobalISel] Legalize vector boolean bitcasts to scalars by lowering via stack.
Reviewers: davemgreen, topperc, arsenm
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/121171
Commit: 34e8aff480dd9cd0372a7c14d13dfca5d3cd1a24
https://github.com/llvm/llvm-project/commit/34e8aff480dd9cd0372a7c14d13dfca5d3cd1a24
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/Support/Recycler.h
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/RecyclerTest.cpp
Log Message:
-----------
[Support] Recycler: Enforce minimum allocation size (#121425)
Recycler uses reinterpret_cast to an internal structure of size 8.
Invalid write occurs if Recycler is used for objects with sizes less
than 8.
Commit: 483832b37a7dd98542dce2ad764ecddc3f0c85b9
https://github.com/llvm/llvm-project/commit/483832b37a7dd98542dce2ad764ecddc3f0c85b9
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Log Message:
-----------
[gn build] Port 34e8aff480dd
Commit: a77346bad0d80a7f7e184f3d6e12c7f532101136
https://github.com/llvm/llvm-project/commit/a77346bad0d80a7f7e184f3d6e12c7f532101136
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[IRBuilder] Refactor FMF interface (#121657)
Up to now, the only way to set specified FMF flags in IRBuilder is to
use `FastMathFlagGuard`. It makes the code ugly and hard to maintain.
This patch introduces a helper class `FMFSource` to replace the original
parameter `Instruction *FMFSource` in IRBuilder. To maximize the
compatibility, it accepts an instruction or a specified FMF.
This patch also removes the use of `FastMathFlagGuard` in some simple
cases.
Compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=f87a9db8322643ccbc324e317a75b55903129b55&to=9397e712f6010be15ccf62f12740e9b4a67de2f4&stat=instructions%3Au
Commit: 5f7568a32c5572e10c8818192a985d7278a261e2
https://github.com/llvm/llvm-project/commit/5f7568a32c5572e10c8818192a985d7278a261e2
Author: Matthias Springer <me at m-sp.org>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Fix mapping in `findOrBuildReplacementValue` (#121644)
Fixes two minor issues in `findOrBuildReplacementValue`:
* Remove a redundant `mapping.map`.
* Map `repl` instead of `value`. We used to overwrite an existing
mapping, which could introduce extra materializations.
Note: We generally do not want to overwrite mappings, but create a chain
of mappings. There are still a few more places, where a mapping is
overwritten. Once those are fixed, I will put an assertion into
`ConversionValueMapping::map`.
Commit: b51a082e1afd707f8cf1473e4c49374e7e951d2d
https://github.com/llvm/llvm-project/commit/b51a082e1afd707f8cf1473e4c49374e7e951d2d
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/Support/Recycler.h
M llvm/unittests/Support/CMakeLists.txt
R llvm/unittests/Support/RecyclerTest.cpp
Log Message:
-----------
Revert "[Support] Recycler: Enforce minimum allocation size" (#121735)
Reverts llvm/llvm-project#121425
Commit: c05599966cd594c15834378f57669719d221c4d4
https://github.com/llvm/llvm-project/commit/c05599966cd594c15834378f57669719d221c4d4
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/copysign.ll
Log Message:
-----------
[InstCombine] Fix FMF propagation in `copysign Mag, (copysign ?, X) -> copysign Mag, X` (#121574)
Closes https://github.com/llvm/llvm-project/issues/121432.
Commit: f99b1907570aa1ac3c8c0ff886563766bbdbc1c8
https://github.com/llvm/llvm-project/commit/f99b1907570aa1ac3c8c0ff886563766bbdbc1c8
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Log Message:
-----------
[gn build] Port b51a082e1afd
Commit: 2b63077cfa13095b3e64f79fe825cc85ca9da7be
https://github.com/llvm/llvm-project/commit/2b63077cfa13095b3e64f79fe825cc85ca9da7be
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/test/CodeGen/X86/2011-06-03-x87chain.ll
M llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll
M llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll
M llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll
M llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll
M llvm/test/CodeGen/X86/StackColoring.ll
M llvm/test/CodeGen/X86/asm-label.ll
M llvm/test/CodeGen/X86/avx-select.ll
M llvm/test/CodeGen/X86/avx512-i1test.ll
M llvm/test/CodeGen/X86/block-placement.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
M llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir
M llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir
M llvm/test/CodeGen/X86/combine-concatvectors.ll
M llvm/test/CodeGen/X86/crash.ll
M llvm/test/CodeGen/X86/domain-reassignment-test.ll
M llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
M llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll
M llvm/test/CodeGen/X86/hoist-spill.ll
M llvm/test/CodeGen/X86/implicit-null-checks.mir
M llvm/test/CodeGen/X86/interval-update-remat.ll
M llvm/test/CodeGen/X86/jump_sign.ll
M llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll
M llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll
M llvm/test/CodeGen/X86/lsr-delayed-fold.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
M llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll
M llvm/test/CodeGen/X86/misched-crash.ll
M llvm/test/CodeGen/X86/pr10475.ll
M llvm/test/CodeGen/X86/pr11998.ll
M llvm/test/CodeGen/X86/pr32108.ll
M llvm/test/CodeGen/X86/pr50254.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shuffle-combine-crash.ll
M llvm/test/CodeGen/X86/stackmap.ll
M llvm/test/CodeGen/X86/swifterror.ll
M llvm/test/CodeGen/X86/switch.ll
M llvm/test/CodeGen/X86/tail-merge-unreachable.ll
M llvm/test/CodeGen/X86/unreachable-loop-sinking.ll
M llvm/test/CodeGen/X86/update-terminator.mir
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
Log Message:
-----------
[llvm] Remove `br i1 undef` from CodeGen/X86 tests (#121733)
This PR removes tests with `br i1 undef` under `llvm/tests/CodeGen/X86`.
There will be more PRs in the future for this directory.
Replacing `undef` with a new function argument doesn't work in some of
the tests, instead, I've replaced them with `poison`.
Commit: efd929efa589d863611473b99c3249c9d0f3f5ed
https://github.com/llvm/llvm-project/commit/efd929efa589d863611473b99c3249c9d0f3f5ed
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
A libclc/Maintainers.md
M llvm/Maintainers.md
Log Message:
-----------
[libclc] Add Maintainers.md for libclc (#118309)
This adds a Maintainers.md files to libclc. Recently I needed to find a
libclc maintainer and I had no idea there was one listed in llvm/
instead of in libclc/.
Commit: b0c0a148dbad9f4d9a2e855deec05669269d30c7
https://github.com/llvm/llvm-project/commit/b0c0a148dbad9f4d9a2e855deec05669269d30c7
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M lldb/docs/use/map.rst
Log Message:
-----------
[lldb][Docs] Add equivalents of GDB's "skip" to command map (#120740)
https://sourceware.org/gdb/current/onlinedocs/gdb.html/Skipping-Over-Functions-and-Files.html
We can't emulate all the features of that command but we can skip a
function by name with some extra steps.
As far as I know this only matches function name unlike GDB that can
filter on file and line and so on:
```
target.process.thread.step-avoid-regexp -- A regular expression defining functions step-in won't stop in.
```
It's likely it's got some corner cases that don't work, maybe inlining,
but it doesn't seem worth going into it here.
I don't think we can chain lldb interpreter commands, so I have shown
the steps separately.
I have also mentioned `thread step-in` and its alias `sif`. Which were
new to me too.
Commit: 7a62a3a8dc91cb5bfebccac3fe509af009383799
https://github.com/llvm/llvm-project/commit/7a62a3a8dc91cb5bfebccac3fe509af009383799
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Fix formatting mistakes in Maintainers.md (NFC)
Commit: 6b81e746bff0c59bfa20fc490c852376092adc1c
https://github.com/llvm/llvm-project/commit/6b81e746bff0c59bfa20fc490c852376092adc1c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update AliasAnalysis maintainers (#120447)
Currently hfinkel is listed as the AliasAnalysis maintainer, but I
believe he hasn't been actively working on LLVM in the last couple of
years, so I'd like to update this information.
I'd like to nominate fhahn and myself as the new maintainers for AA.
While here, I'd also like to nominate alinas as the maintainer for
MemorySSA.
Commit: 2a593bbcf3b022a4ac11a76e03883d6aae2f000c
https://github.com/llvm/llvm-project/commit/2a593bbcf3b022a4ac11a76e03883d6aae2f000c
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/test/CXX/drs/cwg29xx.cpp
Log Message:
-----------
[clang][NFC] Stop testing CWG2917 in C++98 mode
Commit: eff126501efc3981727ef0e918c4dca0fa2eb778
https://github.com/llvm/llvm-project/commit/eff126501efc3981727ef0e918c4dca0fa2eb778
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/test/CXX/drs/cwg0xx.cpp
M clang/test/CXX/drs/cwg14xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg2335.cpp
M clang/test/CXX/drs/cwg23xx.cpp
M clang/test/CXX/drs/cwg24xx.cpp
M clang/test/CXX/drs/cwg25xx.cpp
M clang/test/CXX/drs/cwg26xx.cpp
M clang/test/CXX/drs/cwg28xx.cpp
M clang/test/CXX/drs/cwg29xx.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
Log Message:
-----------
[clang][NFC] Fix expected directives in C++ DRs
If directive is put inside `#if __cplusplus`, it should reflect the condition, instead of being generic `expected`.
Commit: 3c8344f7ba7e33febb93dec40374d55119c8571b
https://github.com/llvm/llvm-project/commit/3c8344f7ba7e33febb93dec40374d55119c8571b
Author: Amara Emerson <amara at apple.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M compiler-rt/cmake/builtin-config-ix.cmake
Log Message:
-----------
[AArch64][SME] Fix broken compiler check for SME2 support in compiler-rt (#121625)
This compile time test uses inline asm with `.arch` directives to set
the target feature. It is however broken and always fails, since each
`asm()` construct in LLVM sets up a new AsmParser, and therefore the
`.arch` directive has no effect on later `asm()` contents. To fix this
we need to use a single inline `asm()` call with the entire code chunk
to emit contained inside.
Commit: 0b73b5af60f2c544892b9dd68b4fa43eeff52fc1
https://github.com/llvm/llvm-project/commit/0b73b5af60f2c544892b9dd68b4fa43eeff52fc1
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
M llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
M llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
M llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
M llvm/test/CodeGen/AArch64/sign-return-address.ll
M llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
Log Message:
-----------
[AArch64] Correct position of CFI Instruction for Pointer Authentication (#121559)
As part #112171, support for FEAT_PAuthLR's CFI instructions was added.
However, the CFI instructions are emitted in the incorrect location. This
leads to incorrect CodeGen being generated and possible issues when
running a program. According to the ABI, the CFI instructions should be
emitted before the signing instruction. This is now done properly.
ABI information can be found here:
https://github.com/ARM-software/abi-aa/blob/bf0e2c8047c70987165f3e05e571d7836370ade9/aadwarf64/aadwarf64.rst#44call-frame-instructions
Commit: 9e4774b934a26489e0e3ae60def3aefb5c73edd3
https://github.com/llvm/llvm-project/commit/9e4774b934a26489e0e3ae60def3aefb5c73edd3
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Add LT_RequiresExpression and LT_SimpleRequirement (#121681)
The new line types help to annotate */&/&& in simple requirements as
binary operators.
Fixes #121675.
Commit: f6bfbc87779ef2079e9b1356ac21381659f13fbb
https://github.com/llvm/llvm-project/commit/f6bfbc87779ef2079e9b1356ac21381659f13fbb
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
Log Message:
-----------
[mlir] flush output in transform.print (#121382)
Print operations are often used for debugging, immediately before the
compiler aborts. In such cases, it is sometimes possible that the output
isn't fully produced yet. Make sure it is by explicitly flushing the
output.
Commit: 3c5f2698b02ae3cec13551226f083984ab41f0f3
https://github.com/llvm/llvm-project/commit/3c5f2698b02ae3cec13551226f083984ab41f0f3
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/test/CXX/drs/cwg0xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg21xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
Log Message:
-----------
[clang][NFC] Stop using atypical compiler arguments in C++ DR tests
Commit: 8e1b49c38edc667b0d740f19b24c9796b948c274
https://github.com/llvm/llvm-project/commit/8e1b49c38edc667b0d740f19b24c9796b948c274
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ComplexDeinterleavingPass.h
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/complex-deinterleaving-cdot.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
Log Message:
-----------
Complex deinterleaving/single reductions build fix Reapply "Add support for single reductions in ComplexDeinterleavingPass (#112875)" (#120441)
This reverts commit 76714be5fd4ace66dd9e19ce706c2e2149dd5716, fixing the
build failure that caused the revert.
The failure stemmed from the complex deinterleaving pass identifying a
series of add operations as a "complex to single reduction", so when it
tried to transform this erroneously identified pattern, it faulted. The
fix applied is to ensure that complex numbers (or patterns that match
them) are used throughout, by checking if there is a deinterleave node
amidst the graph.
Commit: a3fff3a14daefd99760f4a848985b6e971ff4496
https://github.com/llvm/llvm-project/commit/a3fff3a14daefd99760f4a848985b6e971ff4496
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll
Log Message:
-----------
[LoopVectorize][NFC] Fix arith-fp-frem-costs.ll test to use new vplan cost model (#120742)
Commit: 3a7a9c928671adc17046acc3a25e2d9bd5c80fcc
https://github.com/llvm/llvm-project/commit/3a7a9c928671adc17046acc3a25e2d9bd5c80fcc
Author: Dhruv Srivastava <dhruv.srivastava at ibm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
A lldb/include/lldb/Host/aix/HostInfoAIX.h
M lldb/source/Host/CMakeLists.txt
A lldb/source/Host/aix/HostInfoAIX.cpp
Log Message:
-----------
[lldb][AIX] HostInfoAIX Support (#117906)
This PR is in reference to porting LLDB on AIX.
Link to discussions on llvm discourse and github:
1. https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640
2. https://github.com/llvm/llvm-project/issues/101657
The complete changes for porting are present in this draft PR:
https://github.com/llvm/llvm-project/pull/102601
Added a HostInfoAIX file for the AIX platform.
Most of the common functionalities are handled by the parent
HostInfoPosix now,
So we just have some basic functions implemented here.
Commit: d3b77a960dd9edf34a9143003ee2813926c31a7e
https://github.com/llvm/llvm-project/commit/d3b77a960dd9edf34a9143003ee2813926c31a7e
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
Log Message:
-----------
[gn build] Port 3a7a9c928671
Commit: 1feeeb47e56f8551dcd813fbb987bec628970f0d
https://github.com/llvm/llvm-project/commit/1feeeb47e56f8551dcd813fbb987bec628970f0d
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LoopVectorize][NFC] Move "LV: Selecting VF" debug output (#120744)
Move the debug output that prints out the selected VF from
selectVectorizationFactor -> computeBestVF. This means that the output
will still be written even after removing the assert for the legacy and
vplan cost models matching.
Commit: 31340457399d218c27a7a74770eb9fa03e6ae92b
https://github.com/llvm/llvm-project/commit/31340457399d218c27a7a74770eb9fa03e6ae92b
Author: James Chesterman <James.Chesterman at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64][SVE] Add dot product codegen for partial reductions with no binary operation on input (#120207)
Add codegen for when the input type has 4 times as many elements as the
output type and the input to the partial reduction does not have a
binary operation performed on it.
Commit: a13bcf3ced35b0df89ac13670690b4482052e47f
https://github.com/llvm/llvm-project/commit/a13bcf3ced35b0df89ac13670690b4482052e47f
Author: Alejandro Álvarez Ayllón <alejandro.alvarez at sonarsource.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/missing-body-in-import.cpp
Log Message:
-----------
[clang] Do not serialize function definitions without a body (#121550)
An instantiated templated function definition may not have a body due to
parsing errors inside the templated function. When serializing, an
assert is triggered inside `ASTRecordWriter::AddFunctionDefinition`.
The instantiation may happen on an intermediate module.
The test case was reduced from `mp-units`.
Commit: 599c73990532333e62edf8ba19a5302b543f976f
https://github.com/llvm/llvm-project/commit/599c73990532333e62edf8ba19a5302b543f976f
Author: Matthias Springer <me at m-sp.org>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
M mlir/include/mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
A mlir/test/Integration/GPU/CUDA/assert.mlir
Log Message:
-----------
[mlir][GPU] Add NVVM-specific `cf.assert` lowering (#120431)
This commit add an NVIDIA-specific lowering of `cf.assert` to to
`__assertfail`.
Note: `getUniqueFormatGlobalName`, `getOrCreateFormatStringConstant` and
`getOrDefineFunction` are moved to `GPUOpsLowering.h`, so that they can
be reused.
Commit: 4df366cd8080851f83628cedf85f9f84c2db317d
https://github.com/llvm/llvm-project/commit/4df366cd8080851f83628cedf85f9f84c2db317d
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Lower/OpenMP/Todo/omp-declarative-allocate-align.f90
A flang/test/Parser/OpenMP/allocate-align-tree.f90
M flang/test/Parser/OpenMP/allocate-unparse.f90
A flang/test/Semantics/OpenMP/allocate-align01.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[FLANG][OpenMP]Add support for ALIGN clause on OMP ALLOCATE (#120791)
This is trivially additional support for the existing ALLOCATE
directive, which allows an ALIGN clause.
The ALLOCATE directive is currently not implemented, so this is just
addding the necessary parser parts to allow the compiler to not say
"Huh? I don't get this" [or "Expected OpenMP construct"] when it
encounters the ALIGN clause.
Some parser testing is updated and a new todo test, just in case the
feature of align clause is not supported by the initial support for
ALLOCATE.
Commit: e4e2f5369301d0965343406089d63ddfba4c08d0
https://github.com/llvm/llvm-project/commit/e4e2f5369301d0965343406089d63ddfba4c08d0
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/AArch64/sincos.c
M clang/test/CodeGen/X86/math-builtins.c
M clang/test/OpenMP/declare_simd_aarch64.c
Log Message:
-----------
[clang] Add sincos builtin using `llvm.sincos` intrinsic (#114086)
This registers `sincos[f|l]` as a clang builtin and updates GCBuiltin to
emit the `llvm.sincos.*` intrinsic when `-fno-math-errno` is set. Note:
`llvm.sincos.*` is only emitted by `__builtin_sincos[f|l]` functions in
this initial patch.
Commit: ef2afa1e83fad5f813e5d12f4a88acbaf8cf85fe
https://github.com/llvm/llvm-project/commit/ef2afa1e83fad5f813e5d12f4a88acbaf8cf85fe
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M libcxx/include/__type_traits/unwrap_ref.h
M libcxx/include/__utility/pair.h
M libcxx/include/tuple
Log Message:
-----------
[libc++] Simplify unwrap_ref_decay a bit (#121623)
Commit: b359c84f3ad68457048740b3d259258d3722eeed
https://github.com/llvm/llvm-project/commit/b359c84f3ad68457048740b3d259258d3722eeed
Author: Luke Lau <luke at igalia.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
M llvm/test/CodeGen/RISCV/add_shl_constant.ll
Log Message:
-----------
[RISCV] Don't commute with shift if it would break sh{1,2,3}add pattern (#119527)
This fixes a regression from #101294 by checking if we might be
clobbering a sh{1,2,3}add pattern.
Only do this is the underlying add isn't going to be folded away into an
address offset.
Commit: 3bd494dfa6d520e25dc03047c92f28c121293a75
https://github.com/llvm/llvm-project/commit/3bd494dfa6d520e25dc03047c92f28c121293a75
Author: Dhruv Srivastava <dhruv.srivastava at ibm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M lldb/source/Host/posix/DomainSocket.cpp
Log Message:
-----------
[lldb][POSIX] Replace bzero with memset in domain socket code (#121747)
Replace `bzero` with the standard `memset` so that it is common to all platforms.
Commit: 266bb4971b7cb8481bf9f3aa7a9fbba08ec89d98
https://github.com/llvm/llvm-project/commit/266bb4971b7cb8481bf9f3aa7a9fbba08ec89d98
Author: staz <alyystaz at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M polly/docs/UsingPollyWithClang.rst
Log Message:
-----------
[docs] fix grammar mistake (#121695)
Fix a grammar mistake in Polly docs.
Co-authored-by: hstk30-hw <hanwei62 at huawei.com>
Commit: 648e256e541d6421eca72df733f888787485bda8
https://github.com/llvm/llvm-project/commit/648e256e541d6421eca72df733f888787485bda8
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymExpr.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
M clang/lib/StaticAnalyzer/Core/SymbolManager.cpp
M clang/test/Analysis/dump_egraph.cpp
M clang/test/Analysis/expr-inspection-printState-diseq-info.c
M clang/test/Analysis/expr-inspection-printState-eq-classes.c
M clang/test/Analysis/ptr-arith.cpp
M clang/test/Analysis/symbol-simplification-disequality-info.cpp
M clang/test/Analysis/symbol-simplification-fixpoint-one-iteration.cpp
M clang/test/Analysis/symbol-simplification-fixpoint-two-iterations.cpp
M clang/test/Analysis/unary-sym-expr.c
Log Message:
-----------
Reapply "[clang][analyzer] Stable order for SymbolRef-keyed containers" (#121749)
Generalize the SymbolIDs used for SymbolData to all SymExprs and use
these IDs for comparison SymbolRef keys in various containers, such as
ConstraintMap. These IDs are superior to raw pointer values because they
are more controllable and are not randomized across executions (unlike
[pointers](https://en.wikipedia.org/wiki/Address_space_layout_randomization)).
These IDs order is stable across runs because SymExprs are allocated in
the same order.
Stability of the constraint order is important for the stability of the
analyzer results. I evaluated this change on a set of 200+ open-source C
and C++ projects with the total number of ~78 000 symbolic-execution
issues passing Z3 refutation.
This patch reduced the run-to-run churn (flakiness) in SE issues from
80-90 to 30-40 (out of 78K) in our CSA deployment (in our setting flaky
issues are mostly due to Z3 refutation instability).
Note, most of the issue churn (flakiness) is caused by the mentioned Z3
refutation. With Z3 refutation disabled, issue churn goes down to ~10
issues out of 83K and this patch has no effect on appearing/disappearing
issues between runs. It however, seems to reduce the volatility of the
execution flow: before we had 40-80 issues with changed execution flow,
after - 10-30.
Importantly, this change is necessary for the next step in stabilizing
analysis results by caching Z3 query outcomes between analysis runs
(work in progress).
Across our admittedly noisy CI runs, I detected no significant effect on
memory footprint or analysis time.
This PR reapplies https://github.com/llvm/llvm-project/pull/121551 with
a fix to a g++ compiler error reported on some build bots
CPP-5919
Commit: d8d4c187619098ee7b0497b4f40311e3ee1f9259
https://github.com/llvm/llvm-project/commit/d8d4c187619098ee7b0497b4f40311e3ee1f9259
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
M clang/test/CodeGen/AArch64/sme-inline-streaming-attrs.c
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/Inline/AArch64/sme-pstateza-attrs.ll
Log Message:
-----------
[AArch64][SME] Disable inlining of callees with new ZT0 state (#121338)
Inlining must be disabled for new-ZT0 callees as the callee is required
to save ZT0 and toggle PSTATE.ZA on entry.
Commit: 9ce8f4b70b31b031ac9b4818a268bfc8c67a7a8e
https://github.com/llvm/llvm-project/commit/9ce8f4b70b31b031ac9b4818a268bfc8c67a7a8e
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M mlir/include/mlir/IR/Dialect.h
Log Message:
-----------
[mlir] DCE `friend Dialect::registerDialect` (#121728)
Commit: fd6f8b3ce33cc2cbe378f8f1b391f3f40fa7bd54
https://github.com/llvm/llvm-project/commit/fd6f8b3ce33cc2cbe378f8f1b391f3f40fa7bd54
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
Log Message:
-----------
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
This combine pattern perform the below transformation.
fmul x, select(y, A, B) -> fldexp (x, select i32 (y, a, b))
fmul x, select(y, -A, -B) -> fldexp ((fneg x), select i32 (y, a, b))
where, A=2^a & B=2^b ; a and b are integers.
It is a follow-up PR to implement the above combine for globalIsel, as
the corresponding DAG combine has been done for SelectionDAG Isel
(#111109)
Commit: 0c1cf753008f375169c4d3a113b7b4f1120dddba
https://github.com/llvm/llvm-project/commit/0c1cf753008f375169c4d3a113b7b4f1120dddba
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
Log Message:
-----------
[mlir] DCE `RegisteredOperationName::parseAssembly` decl (#121730)
Commit: 67652a3d9fa80dcd940ce8863e32d0a274f7f8e1
https://github.com/llvm/llvm-project/commit/67652a3d9fa80dcd940ce8863e32d0a274f7f8e1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Add horizontal-sub test coverage for #34072
Matches the existing horizontal-add tests, with the additional non-commutable constraint
Commit: 3edbe36c3eb01d1c35ac1761da108e3a493258ee
https://github.com/llvm/llvm-project/commit/3edbe36c3eb01d1c35ac1761da108e3a493258ee
Author: Yihe Li <winmikedows at hotmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/AST/Expr.cpp
M clang/test/SemaCXX/warn-unused-result.cpp
Log Message:
-----------
[clang] Fix missing check for nullptr in CallExpr::getUnusedResultAttr (#118636)
Fixes #117975, a regression introduced by #112521 due to forgetting
to check for `nullptr` before dereferencing in
`CallExpr::getUnusedResultAttr`.
Commit: 8f17c908e3858c0a2a9b1bed3f6506fec3c6f910
https://github.com/llvm/llvm-project/commit/8f17c908e3858c0a2a9b1bed3f6506fec3c6f910
Author: Nico Weber <thakis at chromium.org>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[clang] Expose -f(no-)wrapv as clang-cl option (#120787)
Also move the -fno-wrapv option definition next to the -fwrapv one while
here.
Commit: 346185c42c59c344fcf0d9fd476c85d287181baf
https://github.com/llvm/llvm-project/commit/346185c42c59c344fcf0d9fd476c85d287181baf
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/CodeGen/AArch64/reduce-or-opt.ll
A llvm/test/Transforms/CodeGenPrepare/AArch64/reduce-or-opt.ll
Log Message:
-----------
[AArch64] Improve codegen of vectorised early exit loops (#119534)
Once PR #112138 lands we are able to start vectorising more loops
that have uncountable early exits. The typical loop structure
looks like this:
vector.body:
...
%pred = icmp eq <2 x ptr> %wide.load, %broadcast.splat
...
%or.reduc = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %pred)
%iv.cmp = icmp eq i64 %index.next, 4
%exit.cond = or i1 %or.reduc, %iv.cmp
br i1 %exit.cond, label %middle.split, label %vector.body
middle.split:
br i1 %or.reduc, label %found, label %notfound
found:
ret i64 1
notfound:
ret i64 0
The problem with this is that %or.reduc is kept live after the loop,
and since this is a boolean it typically requires making a copy of
the condition code register. For AArch64 this requires an additional
cset instruction, which is quite expensive for a typical find loop
that only contains 6 or 7 instructions.
This patch attempts to improve the codegen by sinking the reduction
out of the loop to the location of it's user. It's a lot cheaper to
keep the predicate alive if the type is legal and has lots of
registers for it. There is a potential downside in that a little
more work is required after the loop, but I believe this is worth
it since we are likely to spend most of our time in the loop.
Commit: f0247081faac6b4c0cbaa1540fc9c10756e5a42e
https://github.com/llvm/llvm-project/commit/f0247081faac6b4c0cbaa1540fc9c10756e5a42e
Author: JoelWee <32009741+JoelWee at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M libc/src/stdlib/qsort_pivot.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
Fix after #121482 (#121764)
Commit: 1547382033ca156c13fc16c3b2baed7350b6de8e
https://github.com/llvm/llvm-project/commit/1547382033ca156c13fc16c3b2baed7350b6de8e
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
A llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
Log Message:
-----------
[X86] Support lowering of FMINIMUMNUM/FMAXIMUMNUM (#121464)
Commit: 7cdbde70fad454be6a07464befdfd3995287b0fb
https://github.com/llvm/llvm-project/commit/7cdbde70fad454be6a07464befdfd3995287b0fb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/alternate-shuffle-cost.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice.ll
M llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
M llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
M llvm/test/Transforms/VectorCombine/X86/extract-fneg-insert.ll
Log Message:
-----------
[CostModel][X86] getShuffleCost - use processShuffleMasks for all shuffle kinds to legal types (#120599) (#121760)
Now that processShuffleMasks can correctly handle 2 src shuffles, we can completely remove the shuffle kind limits and correctly recognize the number of active subvectors per legalized shuffle - improveShuffleKindFromMask will determine the shuffle kind for each split subvector.
Commit: c630e13676009757400d5c2c22ba3e1f842cf925
https://github.com/llvm/llvm-project/commit/c630e13676009757400d5c2c22ba3e1f842cf925
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstSimplify] Simplify both operands of select before comparing (#121753)
In the simplifySelectWithEquivalence fold, simplify both operands before
comparing them, instead of comparing one simplified operand with a
non-simplified operand. This is slightly more powerful.
Commit: 69ba565734a64bea91062bfd0c5988276b73eb87
https://github.com/llvm/llvm-project/commit/69ba565734a64bea91062bfd0c5988276b73eb87
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll
Log Message:
-----------
[InstCombine] Handle commuted pattern for `((X s/ C1) << C2) + X` (#121737)
Closes https://github.com/llvm/llvm-project/issues/121700
Commit: 3f7905733820851bc4f65cb4af693c3101cbf20d
https://github.com/llvm/llvm-project/commit/3f7905733820851bc4f65cb4af693c3101cbf20d
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/SemaCXX/type-traits.cpp
Log Message:
-----------
[Clang] Make passing incomplete types to builtin type-traits a non-sfinae-friendly error (#121333)
LWG3929 suggests that passing incomplete types to __is_base_of and other
builtins supporting [meta.unary] should result in a non-sfinaeable
error.
This is consistent with GCC's behavior and avoid inconsistency when
using a builtin instead of a standard trait in a concept-definition.
Fixes #121278
Commit: 81fae0d5e3d3378959483ccd7709a212731bff3f
https://github.com/llvm/llvm-project/commit/81fae0d5e3d3378959483ccd7709a212731bff3f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGen/scoped-fence-ops.c
M clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
M clang/test/CodeGenCUDA/atomic-ops.cu
Log Message:
-----------
[Clang][AMDGPU] Stop defaulting to `one-as` for all atomic scopes (#120095)
Summary:
The documentation at
https://llvm.org/docs/AMDGPUUsage.html#memory-scopes states that these
'one-as' modifiers are more specific versions of the scopes that only
apply to a specific address space. This doesn't make sense for fences
which have no associated address space to use, and it's a more
restrictive version the normal scope. This should not tbe the default
behavior, but it is currently emitted in all cases except for
sequentially consistent.
Commit: b79d3b9519620e34f0e223fdb4a6731db6cda88f
https://github.com/llvm/llvm-project/commit/b79d3b9519620e34f0e223fdb4a6731db6cda88f
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
A clang/test/CXX/drs/cwg273.cpp
M clang/test/CXX/drs/cwg2xx.cpp
Log Message:
-----------
[clang][NFC] Move CWG273 test into its own file
Commit: d68ea317ae056d6b8b66ced620eb3d83a4ac13a4
https://github.com/llvm/llvm-project/commit/d68ea317ae056d6b8b66ced620eb3d83a4ac13a4
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/phi.ll
Log Message:
-----------
[InstCombine] Add additional tests for icmp of phi of zext (NFC)
Commit: 14ba3f9d07ea1664497c5d117120fb243ca221aa
https://github.com/llvm/llvm-project/commit/14ba3f9d07ea1664497c5d117120fb243ca221aa
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/test/CXX/drs/cwg0xx.cpp
M clang/test/CXX/drs/cwg14xx.cpp
M clang/test/CXX/drs/cwg15xx.cpp
M clang/test/CXX/drs/cwg17xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg19xx.cpp
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg20xx.cpp
M clang/test/CXX/drs/cwg21xx.cpp
M clang/test/CXX/drs/cwg22xx.cpp
M clang/test/CXX/drs/cwg23xx.cpp
M clang/test/CXX/drs/cwg273.cpp
M clang/test/CXX/drs/cwg27xx.cpp
M clang/test/CXX/drs/cwg2xx.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/drs/cwg9xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang][NFC] Fill in historical data for C++ DRs with 'yes' availability
Commit: 05bd7d22b6754aeb0c781d4ba002357d5de3ec57
https://github.com/llvm/llvm-project/commit/05bd7d22b6754aeb0c781d4ba002357d5de3ec57
Author: arthurqiu <arthurq at nvidia.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Linker/IRMover.cpp
A llvm/test/Linker/Inputs/libdevice-with-wrong-dl.ll
M llvm/test/Linker/cuda-libdevice.ll
Log Message:
-----------
[MLIR] Fix triple mismatch warning for embedded libdevice (#121447)
IRLinker emits warning when linking two modules of different target
triples. The warning is disabled if the source module is libdevice. When
using libdevice embedded in LLVM library via MLIR_NVVM_EMBED_LIBDEVICE,
IRLinker can no longer tell whether the source module is libdevice via
module identifier.
Since `nvptx64-nvidia-gpulibs` is a magic triple that identifies the
libdevice module already, the libdevice filename check is redundant.
This patch fixes the triple mismatch warning by just removing the
filename check.
Commit: 7cb6e6bced8ca5767c3e609f4826982638fd9543
https://github.com/llvm/llvm-project/commit/7cb6e6bced8ca5767c3e609f4826982638fd9543
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M libc/test/src/stdlib/SortingTest.h
Log Message:
-----------
[libc] Fix sort test failing on NVPTX
Summary:
This test uses too much stack and crashes, make the buffer `static` to
push it to `.bss`. This shouldn't change behavior because the tests are
all run single threaded.
Commit: 1229b78f1676d56d0d386a5c4cde8f98a78d0989
https://github.com/llvm/llvm-project/commit/1229b78f1676d56d0d386a5c4cde8f98a78d0989
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/test/CXX/drs/cwg23xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang][NFC] Clean up CWG2396 test
Commit: d993b11b86dcae75b582939337770eaf1c1a228b
https://github.com/llvm/llvm-project/commit/d993b11b86dcae75b582939337770eaf1c1a228b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] Remove superfluous whitespace from debug log comment. NFC.
Commit: 27751c39d41dc937f6b8a127ca562edbba161584
https://github.com/llvm/llvm-project/commit/27751c39d41dc937f6b8a127ca562edbba161584
Author: JoelWee <32009741+JoelWee at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/stdlib/BUILD.bazel
Log Message:
-----------
Update BUILD.bazel after #121482
Commit: 4ebfd43cf008b941d88a61a2c549e9a5291ee017
https://github.com/llvm/llvm-project/commit/4ebfd43cf008b941d88a61a2c549e9a5291ee017
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/bit-checks.ll
Log Message:
-----------
[InstCombine] Always treat inner and/or as bitwise (#121766)
In https://github.com/llvm/llvm-project/pull/116065, we pass `IsLogical`
into `foldBooleanAndOr` when folding inner and/or ops. But it is always
safe to treat them as bitwise if the outer ops are bitwise.
Alive2: https://alive2.llvm.org/ce/z/hULrgH
Closes https://github.com/llvm/llvm-project/issues/121701.
Commit: df67e37e37a7862e1e67f52e01f0c9a019477930
https://github.com/llvm/llvm-project/commit/df67e37e37a7862e1e67f52e01f0c9a019477930
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
Log Message:
-----------
[clang][NFC] clean up the handling of convergence control tokens (#121738)
Commit: 10fb5d2b4be54c779eda80b65a737b9dae2d959b
https://github.com/llvm/llvm-project/commit/10fb5d2b4be54c779eda80b65a737b9dae2d959b
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/test/CXX/drs/cwg2xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add test for CWG203 "Type of address-of-member expression" (#121687)
This patch adds test for
[CWG203](https://cplusplus.github.io/CWG/issues/203.html). Author was
asking to change the type of pointer-to-member expression to be closer
to how it's written as opposed to where the resulting member belongs to,
but was turned down due to backwards compatibility concerns, so we're
testing the status quo.
There are a total of 6 examples in the filing, so I decided to just
throw all of them into the test. I had to turn example 2 into
`constexpr` test that unfortunately requires C++20. Outcomes in example
5 that Tomasz expected are not in line with implementation behavior and
my reading of the Standard. I think he got confused by the fact that
unlike regular pointers, pointers-to-members can be implicitly
_downcasted_, but not upcasted. I left comments in the example.
Commit: 93220e7e06473a11bf48fee26bcea16cc527e5dc
https://github.com/llvm/llvm-project/commit/93220e7e06473a11bf48fee26bcea16cc527e5dc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
A llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
A llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
Log Message:
-----------
RegAllocGreedy: Fix use after free during last chance recoloring (#120697)
Last chance recoloring can delete the current fixed interval
during recursive assignment of interfering live intervals. Check
if the virtual register value was assigned before attempting the
unassignment, as is done in other scenarios. This relies on the fact
that we do not recycle virtual register numbers.
I have only seen this occur in error situations where the allocation
will fail, but I think this can theoretically happen in working
allocations.
This feels very brute force, but I've spent over a week debugging
this and this is what works without any lit regressions. The surprising
piece to me was that unspillable live ranges may be spilled, and
a number of tests rely on optimizations occurring on them. My other
attempts to fixed this mostly revolved around not identifying unspillable
live ranges as snippet copies. I've also discovered we're making some
unproductive live range splits with subranges. If we avoid such splits,
some of the unspillable copies disappear but mandating that be precise
to fix a use after free doesn't sound right.
Commit: ca603d2536f039194141bf3a01e9ee7f60e37406
https://github.com/llvm/llvm-project/commit/ca603d2536f039194141bf3a01e9ee7f60e37406
Author: David Green <david.green at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/test/CodeGen/AArch64/neon-vcmla.c
Log Message:
-----------
[AArch64] Regenerate neon-vcmla.c test. NFC
This removes -O1 from the opt pipeline, using just mem2reg,instsimplify
instead. The target is changed so that the auto update script will apply.
Commit: 21edac25f09faee23015c6a69d95fcbda287efe2
https://github.com/llvm/llvm-project/commit/21edac25f09faee23015c6a69d95fcbda287efe2
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M .github/new-prs-labeler.yml
A clang/include/clang/Basic/BuiltinsSPIRV.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Sema/Sema.h
A clang/include/clang/Sema/SemaSPIRV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/CMakeLists.txt
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaChecking.cpp
A clang/lib/Sema/SemaSPIRV.cpp
A clang/test/CodeGenSPIRV/Builtins/distance.c
A clang/test/SemaSPIRV/BuiltIns/distance-errors.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/distance.ll
A llvm/test/CodeGen/SPIRV/opencl/distance.ll
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
Log Message:
-----------
[SPIRV] Add Target Builtins using Distance ext as an example (#121598)
- Update pr labeler so new SPIRV files get properly labeled.
- Add distance target builtin to BuiltinsSPIRV.td.
- Update TargetBuiltins.h to account for spirv builtins.
- Update clang basic CMakeLists.txt to build spirv builtin tablegen.
- Hook up sema for SPIRV in Sema.h|cpp, SemaSPIRV.h|cpp, and
SemaChecking.cpp.
- Hookup sprv target builtins to SPIR.h|SPIR.cpp target.
- Update GBuiltin.cpp to emit spirv intrinsics when we get the expected
spirv target builtin.
Consensus was reach in this RFC to add both target builtins and pattern
matching:
https://discourse.llvm.org/t/rfc-add-targetbuiltins-for-spirv-to-support-hlsl/83329.
pattern matching will come in a separate pr this one just sets up the
groundwork to do target builtins for spirv.
partially resolves
[#99107](https://github.com/llvm/llvm-project/issues/99107)
Commit: 98b3191a340b03051281e1dc3655a7ffa9ab2311
https://github.com/llvm/llvm-project/commit/98b3191a340b03051281e1dc3655a7ffa9ab2311
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M libc/docs/CMakeLists.txt
R libc/docs/headers/arpa/inet.rst
R libc/docs/headers/assert.rst
R libc/docs/headers/ctype.rst
R libc/docs/headers/errno.rst
R libc/docs/headers/fenv.rst
R libc/docs/headers/float.rst
R libc/docs/headers/inttypes.rst
R libc/docs/headers/locale.rst
R libc/docs/headers/setjmp.rst
R libc/docs/headers/signal.rst
R libc/docs/headers/stdbit.rst
R libc/docs/headers/stdio.rst
R libc/docs/headers/stdlib.rst
R libc/docs/headers/string.rst
R libc/docs/headers/strings.rst
R libc/docs/headers/sys/mman.rst
R libc/docs/headers/threads.rst
R libc/docs/headers/uchar.rst
R libc/docs/headers/wchar.rst
R libc/docs/headers/wctype.rst
M libc/utils/docgen/arpa/inet.yaml
A libc/utils/docgen/strings.yaml
M libc/utils/docgen/sys/mman.yaml
Log Message:
-----------
[libc][docgen] regen docgen via cmake (#119628)
Now, `ninja docs-libc-html` will re-run docgen.
Previously, we would run docgen offline, and commit the result.
Now we no longer need to do that; docgen is invoked from the
dependencies of the `docs-libc-html` target on demand. This
commit removes the dynamically generated .rst files (keeping
the static ones that haven't been converted to docgen), and
fixes up some mistakes I failed to cleanup recently since I
didn't have such automation in place to catch such bugs.
Commit: d00f65c6acd9f0e1ddae83391f55eb9d232d2f9e
https://github.com/llvm/llvm-project/commit/d00f65c6acd9f0e1ddae83391f55eb9d232d2f9e
Author: Michael Toguchi <michael.d.toguchi at intel.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/Driver/Action.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/Action.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Compilation.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Gnu.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/Linux.h
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MSVC.h
A clang/lib/Driver/ToolChains/SYCL.cpp
A clang/lib/Driver/ToolChains/SYCL.h
A clang/test/Driver/sycl-offload-jit.cpp
M llvm/include/llvm/TargetParser/Triple.h
Log Message:
-----------
[Driver][SYCL] Add initial SYCL offload compilation support (#117268)
Introduces the SYCL based toolchain and initial toolchain construction
when using the '-fsycl' option. This option will enable SYCL based
offloading, creating a SPIR-V based IR file packaged into the compiled
host object.
This includes early support for creating the host/device object using
the new offloading model. The device object is created using the
spir64-unknown-unknown target triple.
New/Updated Options:
-fsycl Enables SYCL offloading for host and device
-fsycl-device-only
Enables device only compilation for SYCL
-fsycl-host-only
Enables host only compilation for SYCL
RFC Reference:
https://discourse.llvm.org/t/rfc-sycl-driver-enhancements/74092
This is a reland of: https://github.com/llvm/llvm-project/pull/107493
Commit: 5e0be962feb37b224590e91879f9ac4a1fcacb85
https://github.com/llvm/llvm-project/commit/5e0be962feb37b224590e91879f9ac4a1fcacb85
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll
Log Message:
-----------
[PowerPC] Support PIC Secure PLT for CALL_RM
https://reviews.llvm.org/D111433 introduced PPCISD::CALL_RM for
-frounding-math. -msecure-plt -frounding-math {-fpic,-fPIC} codegen for
PPC32 became incorrect when a function contains function calls but no
global variable references (GlobalBaseReg).
As reported by @q66 , musl/src/dirent/closedir.c implements such a
function, which is miscompiled.
PPCISD::CALL has custom logic to set up the base register
(https://reviews.llvm.org/D42112). Add an extra case for CALL_RM.
While here, improve the test to
* actually test `case PPCISD::CALL`: we need a non-leaf function that
doesn't access global variables (global variables lead to
GlobalBaseReg, which call `getGlobalBaseReg()` as well).
* test `ExternalSymbolSDNode` with a memset.
Supersedes: #72758
Pull Request: https://github.com/llvm/llvm-project/pull/121281
Commit: 55391f85acc7e7a14ea2ef3c1a4bd8f3df990426
https://github.com/llvm/llvm-project/commit/55391f85acc7e7a14ea2ef3c1a4bd8f3df990426
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/test/Analysis/analyzer-config.c
A clang/test/Analysis/z3-crosscheck-max-attempts.cpp
M clang/test/Analysis/z3/D83660.c
R clang/test/Analysis/z3/Inputs/MockZ3_solver_check.c
A clang/test/Analysis/z3/Inputs/MockZ3_solver_check.cpp
M clang/unittests/StaticAnalyzer/Z3CrosscheckOracleTest.cpp
Log Message:
-----------
[analyzer] Retry UNDEF Z3 queries 2 times by default (#120239)
If we have a refutation Z3 query timed out (UNDEF), allow a couple of
retries to improve stability of the query. By default allow 2 retries,
which will give us in maximum of 3 solve attempts per query.
Retries should help mitigating flaky Z3 queries.
See the details in the following RFC:
https://discourse.llvm.org/t/analyzer-rfc-retry-z3-crosscheck-queries-on-timeout/83711
Note that with each attempt, we spend more time per query.
Currently, we have a 15 seconds timeout per query - which are also in
effect for the retry attempts.
---
Why should this help?
In short, retrying queries should bring stability because if a query
runs long
it's more likely that it did so due to some runtime anomaly than it's on
the edge of succeeding. This is because most queries run quick, and the
queries that run long, usually run long by a fair amount.
Consequently, retries should improve the stability of the outcome of the
Z3 query.
In general, the retries shouldn't increase the overall analysis time
because it's really rare we hit the 0.1% of the cases when we would do
retries. But keep in mind that the retry attempts can add up if many
retries are allowed, or the individual query timeout is large.
CPP-5920
Commit: b6960e2a631df38c076cee2845978b0606cea066
https://github.com/llvm/llvm-project/commit/b6960e2a631df38c076cee2845978b0606cea066
Author: rchamala <36907958+rchamala at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M lldb/bindings/python/python-swigsafecast.swig
M lldb/include/lldb/API/SBModule.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
Log Message:
-----------
[lldb][ResolveSourceFileCallback] Update SBModule (#120832)
Summary:
RFC
https://discourse.llvm.org/t/rfc-python-callback-for-source-file-resolution/83545
SBModule will be used for resolve source file callback as Python
function arguments. This diff allows these things.
Can be instantiated from SBPlatform.
Can be passed to/from Python.
Test Plan:
N/A. The next set of diffs in the stack have unittests and shell test
validation
Co-authored-by: Rahul Reddy Chamala <rachamal at fb.com>
Commit: cb5d866feea72e0a846b4e7b921aaf6e70e196f1
https://github.com/llvm/llvm-project/commit/cb5d866feea72e0a846b4e7b921aaf6e70e196f1
Author: Amara Emerson <amara at apple.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/arm_apple_sme_abi.s
Log Message:
-----------
[AArch64][SME] Add Darwin specific SME ABI routines.
Our platform has some constraints that allow us to make assumptions that
aren't generally applicable to other platforms. We keep an entirely separate
.s file for the routines.
Commit: db88071a8b24ad9302659ee88383eea69a732f11
https://github.com/llvm/llvm-project/commit/db88071a8b24ad9302659ee88383eea69a732f11
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/alternate-shuffle-cost.ll
M llvm/test/Analysis/CostModel/X86/reduction.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice.ll
M llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
M llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll
Log Message:
-----------
[CostModel][X86] Attempt to match cheap v4f32 shuffles that map to SHUFPS instruction (#121778)
Avoid always assuming the worst for v4f32 2 input shuffles, and match the SHUFPS pattern where possible - each pair of output elements must come from the same source register.
Commit: d40235ac24175e20988cc879dc515638df0c28c6
https://github.com/llvm/llvm-project/commit/d40235ac24175e20988cc879dc515638df0c28c6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/TableGen/Record.h
Log Message:
-----------
[TableGen] Remove unused functionality from OpInit class. NFC (#121680)
clone, getNumOperands, and getOperand haven't been used for quite some
time. The only remaining useful thing is the common implementation of
getBit.
Commit: fe42e63d7b1bfb356a5209d3ced846695823b623
https://github.com/llvm/llvm-project/commit/fe42e63d7b1bfb356a5209d3ced846695823b623
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M mlir/include/mlir/Analysis/DataFlowFramework.h
Log Message:
-----------
[mlir][NFC] Refactor `eraseState` to take constant time (#121670)
Refactors `analysisStates` to use two nested maps . This prevents
`eraseState` from having to scan through every analysis state which can
be costly when there are many analysis states and/or `eraseState` is
called frequently.
Signed-off-by: Ian Wood <ianwood2024 at u.northwestern.edu>
Commit: 1401703fe42003745e6937efa13078b462a9d706
https://github.com/llvm/llvm-project/commit/1401703fe42003745e6937efa13078b462a9d706
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
Log Message:
-----------
[RISCV] Add Enum for CSR encodings. (#121674)
This allows us to use them in C++ code without needing to do a table
lookup.
Commit: 6b0807fe2b8af7361f98f0f947a3129a6ab79f7e
https://github.com/llvm/llvm-project/commit/6b0807fe2b8af7361f98f0f947a3129a6ab79f7e
Author: Amara Emerson <amara at apple.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
Log Message:
-----------
[AArch64][GlobalISel] Add support for lowering trunc stores of vector bools.
This is essentially a port of TargetLowering::scalarizeVectorStore(), which
is used for the case where we have something like a store of <8 x s8> truncating
to <8 x s1> in memory. The naive lowering is a sequence of extracts to compute
a scalar value to store.
AArch64's DAG implementation has some more smarts to improve this further which
we can do later.
Reviewers: topperc, davemgreen
Pull Request: https://github.com/llvm/llvm-project/pull/121169
Commit: 2d53eaff4aee73605170ce9910cde68fa7a300b2
https://github.com/llvm/llvm-project/commit/2d53eaff4aee73605170ce9910cde68fa7a300b2
Author: Amara Emerson <amara at apple.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
Log Message:
-----------
[AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores.
This case is different from the earlier <8 x i1> case handled because it triggers
a legalization failure in lowerStore() that's intended for scalar code.
It also was triggering incorrect bitcast actions in the AArch64 rules that weren't
expecting truncating stores.
With these two fixed, more cases are handled. The code is still bad, including
some missing load promotion in our combiners that result in dead stores hanging
around at the end of codegen. Again, we can fix these in separate changes.
Reviewers: davemgreen, madhur13490, topperc, arsenm
Reviewed By: davemgreen
Pull Request: https://github.com/llvm/llvm-project/pull/121185
Commit: 0d5c07285f79a2135730c919c7e7b8e2bd9118e7
https://github.com/llvm/llvm-project/commit/0d5c07285f79a2135730c919c7e7b8e2bd9118e7
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaStmtAttr.cpp
A clang/test/AST/HLSL/HLSLControlFlowHint.hlsl
A clang/test/CodeGenHLSL/HLSLControlFlowHint.hlsl
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
A llvm/test/CodeGen/DirectX/HLSLControlFlowHint.ll
A llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
A llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint.ll
Log Message:
-----------
[HLSL] Adding Flatten and Branch if attributes (#116331)
- adding Flatten and Branch to if stmt.
- adding dxil control flow hint metadata generation
- modifing spirv OpSelectMerge to account for the specific attributes.
Closes #70112
---------
Co-authored-by: Joao Saffran <jderezende at microsoft.com>
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: 7a07d8e9dfcf9cbb659883dd539319089563ac5d
https://github.com/llvm/llvm-project/commit/7a07d8e9dfcf9cbb659883dd539319089563ac5d
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M flang/test/Driver/parse-error.ll
Log Message:
-----------
[flang][Driver] Fix flang/test/Driver/parse-error.ll
The error returned from the driver is actually "Could not scan", not
"Could not parse". The reason that the test has been passing is that
the FileCheck's regular expression "{{.*}}" was one of many sources
of problems, and was quoted in the output. The "CHECK" line matched
the quoted line instead of the actual error message.
Commit: 112793a90ec84c31ced9bdacad7ce204e2148d2c
https://github.com/llvm/llvm-project/commit/112793a90ec84c31ced9bdacad7ce204e2148d2c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[DAG] expandUINT_TO_FP - use getShiftAmountConstant helper. NFC.
Don't bother with separate getShiftAmountTy/getConstant calls.
Commit: 923675193b24d3123ece0a3504c7cd49fc7410e9
https://github.com/llvm/llvm-project/commit/923675193b24d3123ece0a3504c7cd49fc7410e9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Log Message:
-----------
[DAG] VectorLegalizer::ExpandUINT_TO_FLOAT- pull out repeated getValueType calls. NFC.
Commit: f3bc8c34c98a4b1a5361c3148eaeebd51151513f
https://github.com/llvm/llvm-project/commit/f3bc8c34c98a4b1a5361c3148eaeebd51151513f
Author: Aidan Goldfarb <47676355+AidanGoldfarb at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
Add SD matchers and unit test coverage for ISD::VECTOR_SHUFFLE (#119592)
This PR resolves #118845. I aimed to mirror the implementation
`m_Shuffle()` in
[PatternMatch.h](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/IR/PatternMatch.h).
Updated
[SDPatternMatch.h](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/CodeGen/SDPatternMatch.h)
- Added `struct m_Mask` to match masks (`ArrayRef<int>`)
- Added two `m_Shuffle` functions. One to match independently of mask,
and one to match considering mask.
- Added `struct SDShuffle_match` to match `ISD::VECTOR_SHUFFLE`
considering mask
Updated
[SDPatternMatchTest.cpp](https://github.com/llvm/llvm-project/blob/main/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp)
- Added `matchVecShuffle` test, which tests the behavior of both
`m_Shuffle()` functions
- - -
I am not sure if my test coverage is complete. I am not sure how to test
a `false` match, simply test against a different instruction? [Other
tests
](https://github.com/llvm/llvm-project/blob/main/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp#L175),
such as for `VSelect`, test against `Select`. I am not sure if there is
an analogous instruction to compare against for `VECTOR_SHUFFLE`. I
would appreciate some pointers in this area. In general, please
liberally critique this PR!
---------
Co-authored-by: Aidan <aidan.goldfarb at mail.mcgill.ca>
Commit: 3f936251d280d039d0a227247afd6884163e8a9a
https://github.com/llvm/llvm-project/commit/3f936251d280d039d0a227247afd6884163e8a9a
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
A clang/test/CodeGenHLSL/debug/rwbuffer_debug_info.hlsl
Log Message:
-----------
[HLSL] Fix debug info generation for RWBuffer types (#119041)
This PR fix the debug infor generation for RWBuffer types.
- This implements the [same fix as
DXC](https://github.com/microsoft/DirectXShaderCompiler/pull/6296).
- Adds the HLSLAttributedResource debug info generation
Closes #118523
---------
Co-authored-by: Joao Saffran <jderezende at microsoft.com>
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: 21c785d7bd84df0b9176d48e7c3e74c914aae05a
https://github.com/llvm/llvm-project/commit/21c785d7bd84df0b9176d48e7c3e74c914aae05a
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang-c/Index.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/AST/ast-print-openacc-set-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-constructs.c
A clang/test/SemaOpenACC/set-construct-ast.cpp
A clang/test/SemaOpenACC/set-construct.cpp
M clang/test/SemaOpenACC/unimplemented-construct.c
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
Log Message:
-----------
[OpenACC] Implement 'set' construct sema
The 'set' construct is another fairly simple one, it doesn't have an
associated statement and only a handful of allowed clauses. This patch
implements it and all the rules for it, allowing 3 of its for clauses.
The only exception is default_async, which will be implemented in a
future patch, because it isn't just being enabled, it needs a complete
new implementation.
Commit: ff24e9a19e3db330dd6412aac9d1d6c0b416697f
https://github.com/llvm/llvm-project/commit/ff24e9a19e3db330dd6412aac9d1d6c0b416697f
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-set-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/set-construct-ast.cpp
M clang/test/SemaOpenACC/set-construct.cpp
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'default_async' sema
A fairly simple one, only valid on the 'set' construct, this clause
takes an int expression. Most of the work was already done as a part of
parsing, so this patch ends up being a lot of infrastructure.
Commit: 7d5376270ae5807a29597a91d7cf59f967ccf39e
https://github.com/llvm/llvm-project/commit/7d5376270ae5807a29597a91d7cf59f967ccf39e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Log Message:
-----------
[AArch64] Migrate from SearchableTable to GenericTable/Enum. NFC (#121661)
SearchableTable is the legacy version that does not appear to be well
documented. Not sure if the plan was to delete it eventually.
We can eventually use the PrimaryKey feature of GenericTable to remove
one of the SearchIndex declarations. This will sort the generated table
by the primary key and remove the separately generated indexing table to
reduce .rodata size.
This patch is just the mechanical migration. The size savings will be
done in follow ups.
Commit: c388da6ed38ba8892edb90803b76bcfe759fe3cf
https://github.com/llvm/llvm-project/commit/c388da6ed38ba8892edb90803b76bcfe759fe3cf
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
Log Message:
-----------
[libc][bazel] Simplify libc_build_rules by grouping release copts (#121630)
Extract all compiler options used to build "release" versions of libc
API functions into a separate helper function, instead of burying this
logic inside libc_function() macro.
With this change, we further split two "flavors" of cc_library()
produced for each libc public function:
* `<function>.__internal__` library used in unit tests is *not* built
with release copts and is thus indistinguishable from regular
libc_support_library(). Arguably, it's a good thing, because all sources
in a unit test are built with the same set of compiler flags, instead of
"franken-build" when a subset of sources is always built with -O3. If a
user needs to run the tests in optimized mode, they should really be
using Bazel invocation-level compile flags instead.
* `<function>` library that libc users can use to construct their own
static archive *is* built with the same release copts as before. There
is a pre-existing problem that its libc_support_library() dependencies
are not built with the same copts. We're not addressing it here now.
Commit: f4bab06c97060088922c5f6f2702bd12fb74c459
https://github.com/llvm/llvm-project/commit/f4bab06c97060088922c5f6f2702bd12fb74c459
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
A libc/config/gpu/amdgpu/config.json
A libc/config/gpu/amdgpu/entrypoints.txt
A libc/config/gpu/amdgpu/headers.txt
R libc/config/gpu/config.json
R libc/config/gpu/entrypoints.txt
R libc/config/gpu/headers.txt
A libc/config/gpu/nvptx/config.json
A libc/config/gpu/nvptx/entrypoints.txt
A libc/config/gpu/nvptx/headers.txt
Log Message:
-----------
[libc] Split AMDGPU and NVPTX configs into separate folders (#120153)
Summary:
This is a holdover from when these targets were merged. They're
basically the same but there's no reason they should be treated as
identical. I think we will live with a little duplication.
Commit: dc0e258fe4d9d97cefdfeefc932e1e9e15dc542d
https://github.com/llvm/llvm-project/commit/dc0e258fe4d9d97cefdfeefc932e1e9e15dc542d
Author: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
M llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
Log Message:
-----------
[AMDGPU] Remove Dwarf encodings for subregisters (#117891)
Previously, registers and subregisters mapped to the same Dwarf
encoding. We don't really have any way to refer to subregisters directly
from Dwarf, the expression emitter should instead use DW_OPs to stencil
out the subregister from the whole register. This was also confusing
tools that need to map back to the llvm reg (e.g. dwarfdump), since
getLLVMRegNum() would arbitrarily return the _LO16 register.
Commit: 6f28b4b5e960e1c4eeebad18b48e667df1e806a8
https://github.com/llvm/llvm-project/commit/6f28b4b5e960e1c4eeebad18b48e667df1e806a8
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/DebugInfo/GSYM/MergedFunctionsInfo.h
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/lib/DebugInfo/GSYM/MergedFunctionsInfo.cpp
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-merged-funcs-dwarf.yaml
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
Log Message:
-----------
[GSYM] Add support for querying merged functions in llvm-gsymutil (#120991)
Adds the ability to lookup and display all merged functions for an
address in llvm-gsymutil.
Now, when `--merged-functions` is used in combination with
`--address/--addresses-from-stdin`, lookup results will contain
information about merged functions, if available.
To support printing merged function information when using the
`--verbose` option, the `LookupResult` data structure also had to be
extended with pointers to the raw function data and raw merged function
data. This is because merged functions share the same address range, so
it's not easy to look up the raw merged function data for a particular
`LookupResult` that is based on a merged function.
Commit: ce831a231a7509b558121808ab03407916bf1dff
https://github.com/llvm/llvm-project/commit/ce831a231a7509b558121808ab03407916bf1dff
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] true16 for v_fma_f16 (#119477)
Support true16 format for v_fma_f16 in MC.
Since we are replacing v_fma_f16 to v_fma_f16_t16/v_fma_f16_fake16 in
Post-GFX11, have to update the CodeGen pattern for v_fma_f16_fake16 to
get CodeGen test passing. There is no pattern modified/created, but just
replacing the v_fma_f16 with fake16 format.
Commit: 97ea0aba15f7f618d7a0caabf0627793563f3850
https://github.com/llvm/llvm-project/commit/97ea0aba15f7f618d7a0caabf0627793563f3850
Author: Markus Böck <markus.boeck02 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
M llvm/test/TableGen/template-args.td
A mlir/test/tblgen-lsp-server/templ-arg-check.test
Log Message:
-----------
[TableGen] Do not exit in template argument check (#121636)
The signature of `CheckTemplateArgValues` implements error handling via
the `bool` return type, yet always returned false. The single possible
error case instead used `PrintFatalError,` which exits the program
afterward.
This behavior is undesirable: It prevents any further errors from being
printed and makes TableGen less usable as a library as it crashes the
entire process (e.g. `tblgen-lsp-server`).
This PR therefore fixes the issue by using `Error` instead and returning
true if an error occurred. All callers already perform proper error
handling.
As `llvm-tblgen` exits on error, a test was also added to the LSP to
ensure it exits normally despite the error.
Commit: 40a00af3ea529aba93b87d666f3090b4686ff9d0
https://github.com/llvm/llvm-project/commit/40a00af3ea529aba93b87d666f3090b4686ff9d0
Author: Nico Weber <thakis at chromium.org>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
Log Message:
-----------
[gn] port 21edac25f09f (BuiltinsSPIRV)
Commit: 4af3332015c8473642a454ae5f521ae709188d4d
https://github.com/llvm/llvm-project/commit/4af3332015c8473642a454ae5f521ae709188d4d
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] true16 for v_cvt_u32_u16 (#120646)
Support true16 format for v_cvt_u32_u16 in MC
Commit: 6e6f89cba0fd70ef1ea8c9abfbdf03d8f69492c4
https://github.com/llvm/llvm-project/commit/6e6f89cba0fd70ef1ea8c9abfbdf03d8f69492c4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M flang/test/Driver/parse-error.ll
Log Message:
-----------
[flang][test] One more fix in flang/test/Driver/parse-error.ll
The file suffix .f95 remained after 7a07d8e9df, change it to .ll.
Commit: 15f30e70eb18340fc422805707870e298d93161f
https://github.com/llvm/llvm-project/commit/15f30e70eb18340fc422805707870e298d93161f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M libcxx/test/benchmarks/numeric/gcd.bench.cpp
Log Message:
-----------
[libc++] Fix the batch size used in the std::gcd benchmark (#120618)
Since that benchmark is testing n*n inputs, the batch size reported to
GoogleBenchmark should be that amount. Otherwise, GoogleBenchmark
reports the timing for calling std::gcd on the whole sequence, which is
misleading.
Commit: cb1c15639f012838ba1ef202aa9c55551e9019ff
https://github.com/llvm/llvm-project/commit/cb1c15639f012838ba1ef202aa9c55551e9019ff
Author: Jannik Glückert <jannik.glueckert at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M libcxx/src/filesystem/operations.cpp
A libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file_procfs.pass.cpp
Log Message:
-----------
[libc++] Use copy_file_range for fs::copy (#109211)
This optimizes `std::filesystem::copy_file` to use the `copy_file_range`
syscall (Linux and FreeBSD) when available. It allows for reflinks on
filesystems such as btrfs, zfs and xfs, and server-side copy for network
filesystems such as NFS.
Commit: 774c22686330f3ca43e48a1b8076eb30ae03dbd8
https://github.com/llvm/llvm-project/commit/774c22686330f3ca43e48a1b8076eb30ae03dbd8
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M lldb/include/lldb/Core/Progress.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/Progress.cpp
M lldb/unittests/Core/ProgressReportTest.cpp
Log Message:
-----------
[LLDB] Add external progress bit category (#120171)
As feedback on #119052, it was recommended I add a new bit to delineate
internal and external progress events. This patch adds this new
category, and sets up Progress.h to support external events via
SBProgress.
Commit: bda7c9ac79fe841d39084f73730d0b3ffa3b101b
https://github.com/llvm/llvm-project/commit/bda7c9ac79fe841d39084f73730d0b3ffa3b101b
Author: Konstantin Varlamov <varconsteq at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M libcxx/docs/Hardening.rst
M libcxx/include/forward_list
A libcxx/test/libcxx/containers/sequences/forwardlist/assert.pass.cpp
Log Message:
-----------
[libc++][hardening] Add checks to `forward_list` element access. (#120858)
In our implementation, failing these checks would result in a null
pointer access rather than an out-of-bounds access.
Commit: fbcf3cb7fe95d9d420b643ce379f7ee2106a6efc
https://github.com/llvm/llvm-project/commit/fbcf3cb7fe95d9d420b643ce379f7ee2106a6efc
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_type.py
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[libclang/python] Add python binding for clang_Cursor_isAnonymousRecordDecl (#120483)
This function allows checking whether a declaration declares an
anonymous union (as opposed to clang_Cursor_isAnonymous, which just
checks if the declaration has a name).
Commit: be21bd9bbf3bc906f9b98ac3de1fc88a4a8ac4b4
https://github.com/llvm/llvm-project/commit/be21bd9bbf3bc906f9b98ac3de1fc88a4a8ac4b4
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
R bolt/test/AArch64/pad-before-funcs.s
Log Message:
-----------
Revert "[BOLT] Add --pad-funcs-before=func:n (#117924)"
14dcf8214f9c66172d17c1cfaec6aec0030748e0 introduced a subtle bug with
the static `FunctionPadding` map.
If either `opts::FunctionPadSpec` or `opts::FunctionPadBeforeSpec` are set,
the map is going to be populated with the respective spec in the first
invocation of `BinaryEmitter::emitFunction`. The subsequent invocations
will pick up the padding from the map irrespective of whether
`opts::FunctionPadSpec` or `opts::FunctionPadBeforeSpec` is passed as a
parameter.
This breaks an internal test, hence reverting the patch.
Commit: 3f1a391b5eb89e53b5d026c417ae6a508d32c808
https://github.com/llvm/llvm-project/commit/3f1a391b5eb89e53b5d026c417ae6a508d32c808
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-merged-funcs-dwarf.yaml
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
Log Message:
-----------
[llvm-gsymutil] Fix broken tests (#121837)
Recently https://github.com/llvm/llvm-project/pull/120991 broke a couple
of tests.
Also `macho-merged-funcs-dwarf.yaml` was already flaky due to some
non-determinism issues.
Fixing the previous code to not break tests and modifying
`macho-merged-funcs-dwarf.yaml` to fix the non-determinism (which will
be resolved later).
Commit: f06d4d9ae501115c20829bab7513a977a71bf53c
https://github.com/llvm/llvm-project/commit/f06d4d9ae501115c20829bab7513a977a71bf53c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
Log Message:
-----------
[gn build] Port d00f65c6acd9
Commit: ec58ad6149fb8813521973d8ba9690276e282373
https://github.com/llvm/llvm-project/commit/ec58ad6149fb8813521973d8ba9690276e282373
Author: Michael Toguchi <michael.d.toguchi at intel.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/SYCL.cpp
M clang/lib/Driver/ToolChains/SYCL.h
M clang/test/Driver/sycl-offload-jit.cpp
Log Message:
-----------
[Driver][SYCL] Address sanitizer and test issue (#121822)
The following commit:
https://github.com/llvm/llvm-project/commit/d00f65c6acd9f0e1ddae83391f55eb9d232d2f9e
Caused sanitizer build issues and also a test issue when using
%clang_cl. Address these problems.
- Use local static array
- Use '--' for clang_cl calls
---------
Co-authored-by: Vitaly Buka <vitalybuka at gmail.com>
Commit: 32d761bbec660c977322afeac1acbafd46008752
https://github.com/llvm/llvm-project/commit/32d761bbec660c977322afeac1acbafd46008752
Author: Simon Wallis <simon.wallis2 at arm.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/test/CodeGen/AArch64/machine-combiner.ll
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
Log Message:
-----------
[AArch64][machine-scheduler][Neoverse-N2] fdiv is blocking (#119206)
For Neoverse-N2, mark FP divide and square root instructions as blocking
their pipeline until complete.
This matches the way that blocking integer divide instructions are
marked.
>From the Software Optimization Guide, section 3.14 Notes:
1. FP divide and square root operations are performed using an iterative
algorithm and block subsequent similar operations to the same pipeline
until complete.
---------
Co-authored-by: Cullen Rhodes <cullen.rhodes at arm.com>
Commit: 4cceea1acc4029c1c2cee85205184387ac361ef7
https://github.com/llvm/llvm-project/commit/4cceea1acc4029c1c2cee85205184387ac361ef7
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
Log Message:
-----------
[libc][bazel] Remove customization from several libc BUILD rules. (#121843)
Get rid of the following arguments to libc_support_library and
libc_function rules:
* `defines` (for raw_mutex.h) - it wasn't used correctly (e.g. didn't
provide actual value for spin count), and we can instead fallback to
defaults set in the header itself (or rely on library-level configure
options).
* `features` - there's no need to disable sanitization for a subset of
memory functions -- it generally should be the vendor / user
responsibility to control it (e.g. don't include instrumented libc
functions in the build, since they would be provided by sanitizer
runtimes instead).
* `local_defines` (for printf_parser) - no longer needed, since
LIBC_COPT_MOCK_ARG_LIST has been removed in
e0be78be427931e94d287002b9c3910f6bc6a22c
This also removes two ad-hoc BUILD rules (strcpy_sanitized and
printf_mock_parser) which are no longer needed and can be replaced by
strcpy and printf_parser, respectively.
Co-authored-by: Alexey Samsonov <samsonov at google.com>
Commit: c8d435f9afac73d31b53cc120678f60ac4922f97
https://github.com/llvm/llvm-project/commit/c8d435f9afac73d31b53cc120678f60ac4922f97
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
Log Message:
-----------
[RISCV] Use ISD::XOR instead of RISCVISD::VMXOR_VL in lowerVectorMaskVecReduction of scalable ISD::VECREDUCE_AND (#121812)
This allows combining the XOR with earlier ISD::ANDs inserted by type
legalization.
Commit: d0c00cf07852ffcd3c3a08126bd85cc119e8de3b
https://github.com/llvm/llvm-project/commit/d0c00cf07852ffcd3c3a08126bd85cc119e8de3b
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
Log Message:
-----------
[LV] Add test case for #121745.
Test for https://github.com/llvm/llvm-project/issues/121745.
Commit: 3874c64418d2a7e36eab9af9253d905b48b36078
https://github.com/llvm/llvm-project/commit/3874c64418d2a7e36eab9af9253d905b48b36078
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M flang/lib/Common/Fortran.cpp
M flang/test/Semantics/cuf10.cuf
Log Message:
-----------
[flang][cuda] Allow constant actual argument for device dummy (#121845)
The reference compiler allows this use case. Note that writing to this
variable would result in CUDA error.
Commit: f9369cc602272796c15de1065a782f812e791df3
https://github.com/llvm/llvm-project/commit/f9369cc602272796c15de1065a782f812e791df3
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
Log Message:
-----------
[VPlan] Make sure last IV increment value is available if needed.
Legalize extract-from-ends using uniform VPReplicateRecipe of wide
inductions to use regular VPReplicateRecipe, so the correct end value
is available.
Fixes https://github.com/llvm/llvm-project/issues/121745.
Commit: 1a435feffcd85c1e7fe30daf1a3995e95860b300
https://github.com/llvm/llvm-project/commit/1a435feffcd85c1e7fe30daf1a3995e95860b300
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
Log Message:
-----------
[HLSL] Fix build warning after #116331 (#121852)
After #116331 is always SpellingNotCalculated,
so I assume doing nothing is expected.
Commit: 8cd94e0b6d18b6b454431ba9481c2489b480baf4
https://github.com/llvm/llvm-project/commit/8cd94e0b6d18b6b454431ba9481c2489b480baf4
Author: MaheshRavishankar <1663364+MaheshRavishankar at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/test/Conversion/AffineToStandard/lower-affine-to-vector.mlir
M mlir/test/Conversion/AffineToStandard/lower-affine.mlir
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Dialect/LLVM/lower-to-llvm-e2e-with-target-tag.mlir
M mlir/test/Dialect/LLVM/lower-to-llvm-e2e-with-top-level-named-sequence.mlir
Log Message:
-----------
[mlir][Affine] Add nsw to lowering of `AffineMulExpr`. (#121535)
Since index operations have no set bitwidth, it is ill-defined to use
signed/unsigned wrapping behavior. The corollary to which is that it is
always safe to add nsw/nuw to lowering of affine ops.
Also add a folder to fold `div(s|u)i (mul (a, v), v) -> a`
Signed-off-by: MaheshRavishankar <mravisha at amd.com>
Commit: 4312075efa02ad861db0a19a0db8e6003aa06965
https://github.com/llvm/llvm-project/commit/4312075efa02ad861db0a19a0db8e6003aa06965
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/FunctionImportUtils.h
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/Utils/FunctionImportUtils.cpp
M llvm/tools/llvm-link/llvm-link.cpp
Log Message:
-----------
[nfc][thinlto] remove unnecessary return from `renameModuleForThinLTO` (#121851)
Same goes for `FunctionImportGlobalProcessing::run`.
The return value was used, but it was always `false`.
Commit: 01e980e792651391dfc3b399dbe300eddbbd0997
https://github.com/llvm/llvm-project/commit/01e980e792651391dfc3b399dbe300eddbbd0997
Author: Julian Lettner <yln at users.noreply.github.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M lldb/source/Plugins/InstrumentationRuntime/ASanLibsanitizers/InstrumentationRuntimeASanLibsanitizers.cpp
M lldb/source/Plugins/InstrumentationRuntime/Utility/ReportRetriever.cpp
Log Message:
-----------
[lldb] Use `Address` to setup breakpoint (#94794)
Use `Address` (instead of `addr_t`) to setup
breakpoint in `ReportRetriever::SetupBreakpoint`.
This is cleaner and the breakpoint should now
survive re-running of the binary.
rdar://124399066
Commit: 4dc34b0d660a52744164a37466ce245764126296
https://github.com/llvm/llvm-project/commit/4dc34b0d660a52744164a37466ce245764126296
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Add BuiltinsSPIRV (for #121598)
Commit: 97097958fdf525e8c14fcdde94231bae72ea2673
https://github.com/llvm/llvm-project/commit/97097958fdf525e8c14fcdde94231bae72ea2673
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
Log Message:
-----------
[Coverage] MCDC: Move findIndependencePairs deferred into MCDCRecord (#121188)
The result of "Independence pairs" is not mergeable. This change makes
defers re-calculation of "Independence pairs" after merging test
vectors.
No apparent behavior changes.
Commit: 90b04bf84ec3315f803a88882ba846e3086ba5e3
https://github.com/llvm/llvm-project/commit/90b04bf84ec3315f803a88882ba846e3086ba5e3
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRV.td
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll
M llvm/test/CodeGen/SPIRV/opencl/degrees.ll
M llvm/test/CodeGen/SPIRV/opencl/radians.ll
Log Message:
-----------
[NFC] fix up typos (#121842)
Fix Tablegen typo to indicate SPIRV and not HLSL
Fix miscellaneous test case typos.
Commit: 7e2ed35104adbf062119c39c4293eb3bc16bc51b
https://github.com/llvm/llvm-project/commit/7e2ed35104adbf062119c39c4293eb3bc16bc51b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
Log Message:
-----------
AMDGPU: Reduce AddedComplexity on canonicalize pattern (#119796)
Pick the minimum complexity required for tests to pass instead of
a giant debug value of 1000.
Commit: f6365a47a1ad9ab6d432f6e40d14a11419e21282
https://github.com/llvm/llvm-project/commit/f6365a47a1ad9ab6d432f6e40d14a11419e21282
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
Log Message:
-----------
AMDGPU: Fix assert on physreg MUBUF rsrc operand (#120815)
The stack case uses a physical register and should not ordinarily
reach here, but strange things happen at -O0. The testcase still
errors because we do not yet attempt to handle arbitrary dynamic
sized allocas yet.
Fixes: SWDEV-503538
Commit: a8f3ebaf11c3745e5123054776eb71755d16f2f9
https://github.com/llvm/llvm-project/commit/a8f3ebaf11c3745e5123054776eb71755d16f2f9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
Log Message:
-----------
AMDGPU: Mark test as XFAIL in expensive_checks builds
One of the tests added in 93220e7e06473a11bf48fee26bcea16cc527e5dc
fails the machine verifier after allocation, but this is a separate
issue.
Commit: 737d6ca44d383bcf33a0605a7d9014027296269a
https://github.com/llvm/llvm-project/commit/737d6ca44d383bcf33a0605a7d9014027296269a
Author: quic_hchandel <165007698+hchandel at users.noreply.github.com>
Date: 2025-01-07 (Tue, 07 Jan 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcicm-invalid.s
A llvm/test/MC/RISCV/xqcicm-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel at qti.qualcomm.com>
Commit: 3d4e558c0e53fc846ffe664d2e12a0fb655fe3f2
https://github.com/llvm/llvm-project/commit/3d4e558c0e53fc846ffe664d2e12a0fb655fe3f2
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-06 (Mon, 06 Jan 2025)
Changed paths:
M .github/new-prs-labeler.yml
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
R bolt/test/AArch64/pad-before-funcs.s
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_type.py
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/Builtins.td
A clang/include/clang/Basic/BuiltinsSPIRV.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Driver/Action.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaOpenACC.h
A clang/include/clang/Sema/SemaSPIRV.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymExpr.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
M clang/lib/AST/Expr.cpp
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/Driver/Action.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Compilation.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Gnu.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/Linux.h
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MSVC.h
A clang/lib/Driver/ToolChains/SYCL.cpp
A clang/lib/Driver/ToolChains/SYCL.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/CMakeLists.txt
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenACC.cpp
A clang/lib/Sema/SemaSPIRV.cpp
M clang/lib/Sema/SemaStmtAttr.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/SymbolManager.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
A clang/test/AST/HLSL/HLSLControlFlowHint.hlsl
A clang/test/AST/ast-print-openacc-set-construct.cpp
M clang/test/Analysis/analyzer-config.c
M clang/test/Analysis/dump_egraph.cpp
M clang/test/Analysis/expr-inspection-printState-diseq-info.c
M clang/test/Analysis/expr-inspection-printState-eq-classes.c
M clang/test/Analysis/ptr-arith.cpp
M clang/test/Analysis/symbol-simplification-disequality-info.cpp
M clang/test/Analysis/symbol-simplification-fixpoint-one-iteration.cpp
M clang/test/Analysis/symbol-simplification-fixpoint-two-iterations.cpp
M clang/test/Analysis/unary-sym-expr.c
A clang/test/Analysis/z3-crosscheck-max-attempts.cpp
M clang/test/Analysis/z3/D83660.c
R clang/test/Analysis/z3/Inputs/MockZ3_solver_check.c
A clang/test/Analysis/z3/Inputs/MockZ3_solver_check.cpp
M clang/test/CXX/drs/cwg0xx.cpp
M clang/test/CXX/drs/cwg14xx.cpp
M clang/test/CXX/drs/cwg15xx.cpp
M clang/test/CXX/drs/cwg17xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg19xx.cpp
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg20xx.cpp
M clang/test/CXX/drs/cwg21xx.cpp
M clang/test/CXX/drs/cwg22xx.cpp
M clang/test/CXX/drs/cwg2335.cpp
M clang/test/CXX/drs/cwg23xx.cpp
M clang/test/CXX/drs/cwg24xx.cpp
M clang/test/CXX/drs/cwg25xx.cpp
M clang/test/CXX/drs/cwg26xx.cpp
A clang/test/CXX/drs/cwg273.cpp
M clang/test/CXX/drs/cwg27xx.cpp
M clang/test/CXX/drs/cwg28xx.cpp
M clang/test/CXX/drs/cwg29xx.cpp
M clang/test/CXX/drs/cwg2xx.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/drs/cwg9xx.cpp
M clang/test/CodeGen/AArch64/neon-vcmla.c
A clang/test/CodeGen/AArch64/sincos.c
M clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
M clang/test/CodeGen/AArch64/sme-inline-streaming-attrs.c
M clang/test/CodeGen/X86/math-builtins.c
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGen/scoped-fence-ops.c
M clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
M clang/test/CodeGenCUDA/atomic-ops.cu
A clang/test/CodeGenHLSL/HLSLControlFlowHint.hlsl
A clang/test/CodeGenHLSL/debug/rwbuffer_debug_info.hlsl
A clang/test/CodeGenSPIRV/Builtins/distance.c
M clang/test/Driver/cl-options.c
M clang/test/Driver/print-supported-extensions-riscv.c
A clang/test/Driver/sycl-offload-jit.cpp
A clang/test/Modules/missing-body-in-import.cpp
M clang/test/OpenMP/declare_simd_aarch64.c
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaCXX/warn-unused-result.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
A clang/test/SemaOpenACC/set-construct-ast.cpp
A clang/test/SemaOpenACC/set-construct.cpp
M clang/test/SemaOpenACC/unimplemented-construct.c
A clang/test/SemaSPIRV/BuiltIns/distance-errors.c
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/StaticAnalyzer/Z3CrosscheckOracleTest.cpp
M clang/www/cxx_dr_status.html
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/arm_apple_sme_abi.s
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Common/Fortran.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/test/Driver/parse-error.ll
A flang/test/Lower/OpenMP/Todo/omp-declarative-allocate-align.f90
A flang/test/Parser/OpenMP/allocate-align-tree.f90
M flang/test/Parser/OpenMP/allocate-unparse.f90
A flang/test/Semantics/OpenMP/allocate-align01.f90
M flang/test/Semantics/cuf10.cuf
A libc/config/gpu/amdgpu/config.json
A libc/config/gpu/amdgpu/entrypoints.txt
A libc/config/gpu/amdgpu/headers.txt
R libc/config/gpu/config.json
R libc/config/gpu/entrypoints.txt
R libc/config/gpu/headers.txt
A libc/config/gpu/nvptx/config.json
A libc/config/gpu/nvptx/entrypoints.txt
A libc/config/gpu/nvptx/headers.txt
M libc/docs/CMakeLists.txt
R libc/docs/headers/arpa/inet.rst
R libc/docs/headers/assert.rst
R libc/docs/headers/ctype.rst
R libc/docs/headers/errno.rst
R libc/docs/headers/fenv.rst
R libc/docs/headers/float.rst
R libc/docs/headers/inttypes.rst
R libc/docs/headers/locale.rst
R libc/docs/headers/setjmp.rst
R libc/docs/headers/signal.rst
R libc/docs/headers/stdbit.rst
R libc/docs/headers/stdio.rst
R libc/docs/headers/stdlib.rst
R libc/docs/headers/string.rst
R libc/docs/headers/strings.rst
R libc/docs/headers/sys/mman.rst
R libc/docs/headers/threads.rst
R libc/docs/headers/uchar.rst
R libc/docs/headers/wchar.rst
R libc/docs/headers/wctype.rst
M libc/src/stdlib/qsort_pivot.h
M libc/test/src/stdlib/SortingTest.h
M libc/utils/docgen/arpa/inet.yaml
A libc/utils/docgen/strings.yaml
M libc/utils/docgen/sys/mman.yaml
A libclc/Maintainers.md
M libcxx/docs/Hardening.rst
M libcxx/include/__type_traits/unwrap_ref.h
M libcxx/include/__utility/pair.h
M libcxx/include/forward_list
M libcxx/include/tuple
M libcxx/src/filesystem/operations.cpp
M libcxx/test/benchmarks/numeric/gcd.bench.cpp
A libcxx/test/libcxx/containers/sequences/forwardlist/assert.pass.cpp
A libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file_procfs.pass.cpp
M lld/MachO/BPSectionOrderer.h
M lldb/bindings/python/python-swigsafecast.swig
M lldb/docs/use/map.rst
M lldb/include/lldb/API/SBModule.h
M lldb/include/lldb/Core/Progress.h
A lldb/include/lldb/Host/aix/HostInfoAIX.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/Progress.cpp
M lldb/source/Host/CMakeLists.txt
A lldb/source/Host/aix/HostInfoAIX.cpp
M lldb/source/Host/posix/DomainSocket.cpp
M lldb/source/Plugins/InstrumentationRuntime/ASanLibsanitizers/InstrumentationRuntimeASanLibsanitizers.cpp
M lldb/source/Plugins/InstrumentationRuntime/Utility/ReportRetriever.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/unittests/Core/ProgressReportTest.cpp
M llvm/Maintainers.md
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/CodeGen/ComplexDeinterleavingPass.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/DebugInfo/GSYM/MergedFunctionsInfo.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/TableGen/Record.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/Utils/FunctionImportUtils.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/lib/DebugInfo/GSYM/MergedFunctionsInfo.cpp
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Utils/FunctionImportUtils.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/X86/alternate-shuffle-cost.ll
M llvm/test/Analysis/CostModel/X86/reduction.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
A llvm/test/CodeGen/AArch64/complex-deinterleaving-cdot.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
M llvm/test/CodeGen/AArch64/machine-combiner.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
A llvm/test/CodeGen/AArch64/reduce-or-opt.ll
M llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
M llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
M llvm/test/CodeGen/AArch64/sign-return-address.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
A llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
A llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
A llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
A llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
A llvm/test/CodeGen/DirectX/HLSLControlFlowHint.ll
M llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
M llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll
M llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
M llvm/test/CodeGen/RISCV/add_shl_constant.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/distance.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll
M llvm/test/CodeGen/SPIRV/opencl/degrees.ll
A llvm/test/CodeGen/SPIRV/opencl/distance.ll
M llvm/test/CodeGen/SPIRV/opencl/radians.ll
A llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
A llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint.ll
M llvm/test/CodeGen/X86/2011-06-03-x87chain.ll
M llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll
M llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll
M llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll
M llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll
M llvm/test/CodeGen/X86/StackColoring.ll
M llvm/test/CodeGen/X86/asm-label.ll
M llvm/test/CodeGen/X86/avx-select.ll
M llvm/test/CodeGen/X86/avx512-i1test.ll
M llvm/test/CodeGen/X86/block-placement.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
M llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir
M llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir
M llvm/test/CodeGen/X86/combine-concatvectors.ll
M llvm/test/CodeGen/X86/crash.ll
M llvm/test/CodeGen/X86/domain-reassignment-test.ll
M llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
A llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll
M llvm/test/CodeGen/X86/hoist-spill.ll
M llvm/test/CodeGen/X86/implicit-null-checks.mir
M llvm/test/CodeGen/X86/interval-update-remat.ll
M llvm/test/CodeGen/X86/jump_sign.ll
M llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll
M llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll
M llvm/test/CodeGen/X86/lsr-delayed-fold.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
M llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll
M llvm/test/CodeGen/X86/misched-crash.ll
M llvm/test/CodeGen/X86/pr10475.ll
M llvm/test/CodeGen/X86/pr11998.ll
M llvm/test/CodeGen/X86/pr32108.ll
M llvm/test/CodeGen/X86/pr50254.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shuffle-combine-crash.ll
M llvm/test/CodeGen/X86/stackmap.ll
M llvm/test/CodeGen/X86/swifterror.ll
M llvm/test/CodeGen/X86/switch.ll
M llvm/test/CodeGen/X86/tail-merge-unreachable.ll
M llvm/test/CodeGen/X86/unreachable-loop-sinking.ll
M llvm/test/CodeGen/X86/update-terminator.mir
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
A llvm/test/Linker/Inputs/libdevice-with-wrong-dl.ll
M llvm/test/Linker/cuda-libdevice.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
A llvm/test/MC/RISCV/xqcicm-invalid.s
A llvm/test/MC/RISCV/xqcicm-valid.s
M llvm/test/TableGen/template-args.td
A llvm/test/Transforms/CodeGenPrepare/AArch64/reduce-or-opt.ll
M llvm/test/Transforms/Inline/AArch64/sme-pstateza-attrs.ll
M llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/bit-checks.ll
M llvm/test/Transforms/InstCombine/copysign.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
A llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
M llvm/test/Transforms/VectorCombine/X86/extract-fneg-insert.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-merged-funcs-dwarf.yaml
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M mlir/docs/Tutorials/Toy/Ch-2.md
M mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
M mlir/include/mlir/Analysis/DataFlowFramework.h
M mlir/include/mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h
M mlir/include/mlir/IR/Dialect.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/AffineToStandard/lower-affine-to-vector.mlir
M mlir/test/Conversion/AffineToStandard/lower-affine.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Dialect/LLVM/lower-to-llvm-e2e-with-target-tag.mlir
M mlir/test/Dialect/LLVM/lower-to-llvm-e2e-with-top-level-named-sequence.mlir
A mlir/test/Integration/GPU/CUDA/assert.mlir
A mlir/test/tblgen-lsp-server/templ-arg-check.test
M polly/docs/UsingPollyWithClang.rst
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
M utils/bazel/llvm-project-overlay/libc/test/src/stdlib/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
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