[all-commits] [llvm/llvm-project] 978de2: [SPIR-V] Add saturation and float rounding mode de...
Vyacheslav Levytskyy via All-commits
all-commits at lists.llvm.org
Mon Dec 16 01:30:09 PST 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 978de2d6664a74864471d62244700c216fdc6741
https://github.com/llvm/llvm-project/commit/978de2d6664a74864471d62244700c216fdc6741
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll
M llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
Log Message:
-----------
[SPIR-V] Add saturation and float rounding mode decorations, a subset of arithmetic constrained floating-point intrinsics, and SPV_INTEL_float_controls2 extension (#119862)
This PR adds the following features:
* saturation and float rounding mode decorations,
* arithmetic constrained floating-point intrinsics (strict_fadd,
strict_fsub, strict_fmul, strict_fdiv, strict_frem, strict_fma and
strict_fldexp),
* and SPV_INTEL_float_controls2 extension,
* using recent improvements of emit-intrinsics step, this PR also
simplifies pre- and post-legalizer steps and improves instruction
selection.
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