[all-commits] [llvm/llvm-project] 4dac0d: [LLD][ELF] Fix SHF_MERGE misalignment when spilled...
Michael Kruse via All-commits
all-commits at lists.llvm.org
Wed Dec 11 10:29:01 PST 2024
Branch: refs/heads/users/meinersbur/flang_runtime_move-files
Home: https://github.com/llvm/llvm-project
Commit: 4dac0dff086090d071fc3ef60d7458b3d6cfde60
https://github.com/llvm/llvm-project/commit/4dac0dff086090d071fc3ef60d7458b3d6cfde60
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M lld/ELF/OutputSections.cpp
M lld/test/ELF/linkerscript/section-class.test
Log Message:
-----------
[LLD][ELF] Fix SHF_MERGE misalignment when spilled (#119289)
Section merging can increase section alignment after potential spill
sections are created. Since this operation is never performed on spill
sections, they can keep their earlier, smaller, alignment, which
produces a misalignment if a spill occurs.
This change propagates alignment increases forward after merging.
Commit: 7eb73b95cb336cde14d5c755a09cd880bd3d5df9
https://github.com/llvm/llvm-project/commit/7eb73b95cb336cde14d5c755a09cd880bd3d5df9
Author: David Olsen <dolsen at nvidia.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/include/clang/CIR/CIRGenerator.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
Log Message:
-----------
[CIR] Cleanup: mlirContext and astContext (#119450)
ClangIR CodeGen code uses both `mlir::MLIRContext` and
`clang::ASTContext` objects extensively. Refering to either of those as
just "context" can be confusing.
Change the names of all variables, parameters, and fields in
`clang/lib/CIR/CodeGen` that refer to `MLIRContext` or an `ASTContext`
to be either `mlirContext` or `astContext`.
This change is only the renaming of variables/parameters/fields. There
are no behavior changes. So there are no new tests or changes to
existing tests. This change mimics a recent change in the ClangIR
incubator repository.
Commit: 9bb29c3dc19aad6d89fc4bfc488479d8b74ee4ff
https://github.com/llvm/llvm-project/commit/9bb29c3dc19aad6d89fc4bfc488479d8b74ee4ff
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV][VLOPT] Add support for bitwise logical, single width shift, and vector move (#119412)
Add support and tests for these instructions. Get operand info test
exist in llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Commit: e7e42ef116194f987672b3ed38ddbbfc0150b563
https://github.com/llvm/llvm-project/commit/e7e42ef116194f987672b3ed38ddbbfc0150b563
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
Log Message:
-----------
[NFC] Cleanup comments in HLSLExternalSemaSource.cpp (#119444)
Cleaning up some comments that @bogner pointed out were unpolished.
Commit: 5a930339a5330dbab23d9eac28a609df9aa9c3fc
https://github.com/llvm/llvm-project/commit/5a930339a5330dbab23d9eac28a609df9aa9c3fc
Author: ChiaHungDuan <chiahungduan at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/list.h
Log Message:
-----------
[scudo] Minor refactor on element address validation (NFC) (#119436)
Commit: 850c932f058ee0c8a3b31393cf485c15b0cdb74e
https://github.com/llvm/llvm-project/commit/850c932f058ee0c8a3b31393cf485c15b0cdb74e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
Log Message:
-----------
[flang][cuda] Walk through cuf kernel for implicit globals (#119455)
Globals used in cuf kernel need to be flagged as well.
Commit: bedbafff2d459811808b6fa0c75de3ae8a56e7f0
https://github.com/llvm/llvm-project/commit/bedbafff2d459811808b6fa0c75de3ae8a56e7f0
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Fix lit tests with bazel 8.x (#119462)
https://github.com/llvm/llvm-project/issues/83066
Commit: 5d0957fc23b88ec6d3b743eb2b9ad060e528913d
https://github.com/llvm/llvm-project/commit/5d0957fc23b88ec6d3b743eb2b9ad060e528913d
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/lit_test.bzl
Log Message:
-----------
[bazel] Allow overriding py_test rule for lit_test (#119460)
This allows replacing this implementation with another one, such as the
one from aspect_rules_py
Commit: 8c3a8c2619122488812cf050a903314f466b07fb
https://github.com/llvm/llvm-project/commit/8c3a8c2619122488812cf050a903314f466b07fb
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/strings/BUILD.bazel
Log Message:
-----------
[bazel][libc] fix typo in comment
Link: #119433
Commit: cf27e8ea04c39a0f20d465563241bdf2872f2bd7
https://github.com/llvm/llvm-project/commit/cf27e8ea04c39a0f20d465563241bdf2872f2bd7
Author: arthurqiu <arthurq at nvidia.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M mlir/lib/Conversion/GPUToNVVM/CMakeLists.txt
Log Message:
-----------
[mlir][LLVM] Fix missing MLIRNVGPUDialect dependency for MLIRGPUToNVVMTransforms (#119306)
This patch adds the missing MLIRNVGPUDialect dependency for
MLIRGPUToNVVMTransforms, which comes from
[LowerGpuOpsToNVVMOps.cpp](https://github.com/llvm/llvm-project/blob/7498eaa9abf2e4ac0c10fa9a02576d708cc1b624/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp#L34)
Commit: a2fb70523ac310af6d8a4d9663dfe7c9cd370c53
https://github.com/llvm/llvm-project/commit/a2fb70523ac310af6d8a4d9663dfe7c9cd370c53
Author: Sylvestre Ledru <sylvestre at debian.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
R lldb/include/lldb/DataFormatters/FormatterSection.h
M lldb/include/lldb/DataFormatters/FormattersHelpers.h
M lldb/include/lldb/DataFormatters/TypeSummary.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBTypeSummary.cpp
M lldb/source/Core/Section.cpp
M lldb/source/DataFormatters/CMakeLists.txt
R lldb/source/DataFormatters/FormatterBytecode.cpp
R lldb/source/DataFormatters/FormatterBytecode.def
R lldb/source/DataFormatters/FormatterBytecode.h
R lldb/source/DataFormatters/FormatterSection.cpp
M lldb/source/DataFormatters/TypeSummary.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
M lldb/source/Symbol/ObjectFile.cpp
M lldb/source/Target/Target.cpp
R lldb/test/API/functionalities/data-formatter/bytecode-summary/Makefile
R lldb/test/API/functionalities/data-formatter/bytecode-summary/TestBytecodeSummary.py
R lldb/test/API/functionalities/data-formatter/bytecode-summary/main.cpp
M lldb/unittests/DataFormatter/CMakeLists.txt
R lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp
Log Message:
-----------
Revert "[lldb] Add cast to fix compile error on 32-bit platforms"
This reverts commit f6012a209dca6b1866d00e6b4f96279469884320.
Revert "[lldb] Add cast to fix compile error on 32-but platforms"
This reverts commit d300337e93da4ed96b044557e4b0a30001967cf0.
Revert "[lldb] Improve log message to include missing strings"
This reverts commit 0be33484853557bc0fd9dfb94e0b6c15dda136ce.
Revert "[lldb] Add comment"
This reverts commit e2bb47443d2e5c022c7851dd6029e3869fc8835c.
Revert "[lldb] Implement a formatter bytecode interpreter in C++"
This reverts commit 9a9c1d4a6155a96ce9be494cec7e25731d36b33e.
Commit: cafb6b99bb2314c53683870e4130633fff25360a
https://github.com/llvm/llvm-project/commit/cafb6b99bb2314c53683870e4130633fff25360a
Author: vporpo <vporpodas at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
Log Message:
-----------
[SandboxVec][DAG] Update MemDGNode chain upon instr deletion (#118921)
Commit: 67bd04facf48206c1e3a4c2664c2240e787bd6af
https://github.com/llvm/llvm-project/commit/67bd04facf48206c1e3a4c2664c2240e787bd6af
Author: Thurston Dang <thurston at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGen/ubsan-trap-merge.c
M clang/test/CodeGenCXX/catch-undef-behavior.cpp
Log Message:
-----------
[ubsan] Don't merge non-trap handlers if -ubsan-unique-traps or not optimized (#119302)
UBSan handler calls are sometimes merged by the backend, which complicates debugging. Merging is currently disabled for UBSan traps if -ubsan-unique-traps is specified or if optimization is disabled. This patch applies the same policy to non-trap handler calls.
N.B. "-ubsan-unique-traps" becomes somewhat of a misnomer since it will now apply to non-trap handler calls as well as traps; nonetheless, we keep the naming for backwards compatibility.
Commit: c4873819a98f59ce4e2664f94c73c2dfec3393f8
https://github.com/llvm/llvm-project/commit/c4873819a98f59ce4e2664f94c73c2dfec3393f8
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119122)
Commit: 4027e2f248044d944aaf3d9bc9c8eb6928506d44
https://github.com/llvm/llvm-project/commit/4027e2f248044d944aaf3d9bc9c8eb6928506d44
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
A llvm/test/Transforms/Inline/promote-call-bitwidth.ll
Log Message:
-----------
CallPromotionUtils: Correctly use IndexSize when determining the bit width of pointer offsets. (#119138)
Co-authored-by: Alexander Richardson <alexander.richardson at cl.cam.ac.uk>
Commit: 377d1f0a6b862183b25701cc765fca7f84ea8e32
https://github.com/llvm/llvm-project/commit/377d1f0a6b862183b25701cc765fca7f84ea8e32
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
Log Message:
-----------
UncountedLocalVarsChecker and UncheckedLocalVarsChecker should recognize signletons. (#119339)
It's safe to have a raw pointer or a raw reference to a singleton
object. Explicitly allow this in UncountedLocalVarsChecker and
UncheckedLocalVarsChecker.
Commit: 609899f443223ccc977c25293931067e73ad76db
https://github.com/llvm/llvm-project/commit/609899f443223ccc977c25293931067e73ad76db
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
Log Message:
-----------
[flang][cuda] Avoid stack corruption when setting kernel launch parameters (#119469)
In order to get the pointer to a structure member, `getelementptr`
typically requires two indices: one to indicate the structure itself,
and another to specify the member's position. We are missing the former
in `GPULaunchKernelConversion`, so generated code may cause stack
corruption. This PR corrects the indices of a structure used as a kernel
launch temp.
Commit: 9b6bb8386001a1d308cda42fe273733e58b8e93e
https://github.com/llvm/llvm-project/commit/9b6bb8386001a1d308cda42fe273733e58b8e93e
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
R llvm/test/Transforms/Inline/promote-call-bitwidth.ll
Log Message:
-----------
Revert "CallPromotionUtils: Correctly use IndexSize when determining the bit width of pointer offsets. (#119138)"
Reverting due to ASAN bootstrap failures.
This reverts commit 4027e2f248044d944aaf3d9bc9c8eb6928506d44.
Commit: 918d4558b0bad366ecadd411ed48cf64728c68d7
https://github.com/llvm/llvm-project/commit/918d4558b0bad366ecadd411ed48cf64728c68d7
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M libcxxabi/src/demangle/ItaniumDemangle.h
M libcxxabi/test/test_demangle.pass.cpp
M llvm/include/llvm/Demangle/ItaniumDemangle.h
Log Message:
-----------
[libc++abi] Enable demangling of `cp` expression production (#114882)
See itanium-cxx-abi/cxx-abi#196
Commit: 87659a17d0703c1244211d9f8d1f0c21e816f0e1
https://github.com/llvm/llvm-project/commit/87659a17d0703c1244211d9f8d1f0c21e816f0e1
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
A lldb/include/lldb/DataFormatters/FormatterSection.h
M lldb/include/lldb/DataFormatters/FormattersHelpers.h
M lldb/include/lldb/DataFormatters/TypeSummary.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBTypeSummary.cpp
M lldb/source/Core/Section.cpp
M lldb/source/DataFormatters/CMakeLists.txt
A lldb/source/DataFormatters/FormatterBytecode.cpp
A lldb/source/DataFormatters/FormatterBytecode.def
A lldb/source/DataFormatters/FormatterBytecode.h
A lldb/source/DataFormatters/FormatterSection.cpp
M lldb/source/DataFormatters/TypeSummary.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
M lldb/source/Symbol/ObjectFile.cpp
M lldb/source/Target/Target.cpp
A lldb/test/API/functionalities/data-formatter/bytecode-summary/Makefile
A lldb/test/API/functionalities/data-formatter/bytecode-summary/TestBytecodeSummary.py
A lldb/test/API/functionalities/data-formatter/bytecode-summary/main.cpp
M lldb/unittests/DataFormatter/CMakeLists.txt
A lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp
Log Message:
-----------
Reland: [lldb] Implement a formatter bytecode interpreter in C++
Compared to the python version, this also does type checking and error
handling, so it's slightly longer, however, it's still comfortably
under 500 lines.
Relanding with more explicit type conversions.
Commit: e940353fd2ac9817d3506744b309d857e76c0afa
https://github.com/llvm/llvm-project/commit/e940353fd2ac9817d3506744b309d857e76c0afa
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
Revert "CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119122)"
Reverting due to UBSan failures in X86RegisterInfo::getLargestLegalSuperClass
This reverts commit c4873819a98f59ce4e2664f94c73c2dfec3393f8.
Commit: 54ca1c4212e7ff3df880adb1a04dc3d41c033681
https://github.com/llvm/llvm-project/commit/54ca1c4212e7ff3df880adb1a04dc3d41c033681
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix idempotent format of hash in macro body (#118513)
Fixes #118334.
Commit: bdd82d51563717f2d8e6662ab075856b52330971
https://github.com/llvm/llvm-project/commit/bdd82d51563717f2d8e6662ab075856b52330971
Author: Amara Emerson <amara at apple.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/Combine.td
Log Message:
-----------
[GlobalISel] Convert unary propagate_undef_any_op opcodes to use new match syntax. NFC. (#119475)
Commit: 1593f36935edc97bede71bd1d722edf83eaf16a4
https://github.com/llvm/llvm-project/commit/1593f36935edc97bede71bd1d722edf83eaf16a4
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M lldb/source/DataFormatters/FormatterBytecode.cpp
Log Message:
-----------
[lldb] Add explicit type conversion
Commit: c00a708fc954f450679bf0e171029f8da4841cfb
https://github.com/llvm/llvm-project/commit/c00a708fc954f450679bf0e171029f8da4841cfb
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M lldb/source/DataFormatters/FormatterBytecode.cpp
Log Message:
-----------
[lldb] Eliminate dead code (NFC)
Commit: 20e904950967c125abc1e91f57e5a373987ff016
https://github.com/llvm/llvm-project/commit/20e904950967c125abc1e91f57e5a373987ff016
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExternalASTSource.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExternalASTSource.cpp
M clang/lib/AST/ODRHash.cpp
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Serialization/ASTCommon.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderInternals.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/CMakeLists.txt
A clang/lib/Serialization/TemplateArgumentHasher.cpp
A clang/lib/Serialization/TemplateArgumentHasher.h
M clang/test/Modules/cxx-templates.cpp
M clang/test/Modules/odr_hash.cpp
A clang/test/Modules/recursive-instantiations.cppm
M clang/test/OpenMP/target_parallel_ast_print.cpp
M clang/test/OpenMP/target_teams_ast_print.cpp
M clang/test/OpenMP/task_ast_print.cpp
M clang/test/OpenMP/teams_ast_print.cpp
M clang/unittests/Serialization/CMakeLists.txt
A clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h
Log Message:
-----------
[Serialization] Support loading template specializations lazily (#119333)
Reland https://github.com/llvm/llvm-project/pull/83237
---
(Original comments)
Currently all the specializations of a template (including
instantiation, specialization and partial specializations) will be
loaded at once if we want to instantiate another instance for the
template, or find instantiation for the template, or just want to
complete the redecl chain.
This means basically we need to load every specializations for the
template once the template declaration got loaded. This is bad since
when we load a specialization, we need to load all of its template
arguments. Then we have to deserialize a lot of unnecessary
declarations.
For example,
```
// M.cppm
export module M;
export template <class T>
class A {};
export class ShouldNotBeLoaded {};
export class Temp {
A<ShouldNotBeLoaded> AS;
};
// use.cpp
import M;
A<int> a;
```
We have a specialization ` A<ShouldNotBeLoaded>` in `M.cppm` and we
instantiate the template `A` in `use.cpp`. Then we will deserialize
`ShouldNotBeLoaded` surprisingly when compiling `use.cpp`. And this
patch tries to avoid that.
Given that the templates are heavily used in C++, this is a pain point
for the performance.
This patch adds MultiOnDiskHashTable for specializations in the
ASTReader. Then we will only deserialize the specializations with the
same template arguments. We made that by using ODRHash for the template
arguments as the key of the hash table.
To review this patch, I think `ASTReaderDecl::AddLazySpecializations`
may be a good entry point.
Commit: 7987f478be6d9550a6b897536139b4ca82ff03ec
https://github.com/llvm/llvm-project/commit/7987f478be6d9550a6b897536139b4ca82ff03ec
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Serialization/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
Log Message:
-----------
[gn build] Port 20e904950967
Commit: ea76b2d8d83d6885bf5707832cbc4b7655e21b08
https://github.com/llvm/llvm-project/commit/ea76b2d8d83d6885bf5707832cbc4b7655e21b08
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/lib/Driver/XRayArgs.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_interface.cpp
A compiler-rt/lib/xray/xray_riscv.cpp
A compiler-rt/lib/xray/xray_trampoline_riscv32.S
A compiler-rt/lib/xray/xray_trampoline_riscv64.S
A compiler-rt/lib/xray/xray_trampoline_riscv_common.S
M compiler-rt/lib/xray/xray_tsc.h
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/XRay/InstrumentationMap.cpp
A llvm/test/CodeGen/RISCV/xray-attribute-instrumentation.ll
Log Message:
-----------
[XRay][RISCV] RISCV support for XRay (#117368)
Add RISC-V support for XRay. The RV64 implementation has been tested in
both QEMU and in our hardware environment.
Currently this requires D and C extensions, but since both RV64GC and
RVA22/RVA23 are becoming mainstream, I don't think this requirement will
be a big problem.
Based on the previous work by @a-poduval :
https://reviews.llvm.org/D117929
---------
Co-authored-by: Ashwin Poduval <ashwin.poduval at gmail.com>
Commit: b759020cc85d023583c948aa93905e38897b2c0a
https://github.com/llvm/llvm-project/commit/b759020cc85d023583c948aa93905e38897b2c0a
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
Log Message:
-----------
[LV][EVL] Support cast instruction with EVL-vectorization (#108351)
Commit: 51a0c1bf257697fc0b9676e121a73387a40ca6b7
https://github.com/llvm/llvm-project/commit/51a0c1bf257697fc0b9676e121a73387a40ca6b7
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/fix-113880.ll
Log Message:
-----------
[SLP] NFC. Replace TreeEntry::setOperandsInOrder with VLOperands. (#118949)
To reduce repeated code, TreeEntry::setOperandsInOrder will be replaced
by VLOperands.
Arg_size will be provided to make sure other operands will not be
reorderd when VL[0] is IntrinsicInst (because APO is a boolean value).
In addition, BoUpSLP::reorderInputsAccordingToOpcode will also be
removed since it is simple.
Commit: 4b3a878e8a24c13f8dc435e91304d8692d8cb42b
https://github.com/llvm/llvm-project/commit/4b3a878e8a24c13f8dc435e91304d8692d8cb42b
Author: Karthika Devi C <quic_kartc at quicinc.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/test/CodeGen/LoopParallelMD/single_loop_param_parallel.ll
M polly/test/CodeGen/MemAccess/codegen_address_space.ll
M polly/test/CodeGen/MemAccess/create_arrays.ll
M polly/test/CodeGen/MemAccess/different_types.ll
M polly/test/CodeGen/MemAccess/generate-all.ll
M polly/test/CodeGen/OpenMP/alias-metadata.ll
M polly/test/CodeGen/OpenMP/new_multidim_access.ll
M polly/test/CodeGen/RuntimeDebugBuilder/combine_different_values.ll
M polly/test/CodeGen/annotated_alias_scopes.ll
M polly/test/CodeGen/non-affine-phi-node-expansion-2.ll
M polly/test/CodeGen/non_affine_float_compare.ll
M polly/test/CodeGen/partial_write_array.ll
M polly/test/CodeGen/partial_write_impossible_restriction.ll
M polly/test/CodeGen/phi_loop_carried_float.ll
M polly/test/CodeGen/phi_loop_carried_float_escape.ll
M polly/test/CodeGen/scev-backedgetaken.ll
M polly/test/CodeGen/stmt_split_no_dependence.ll
M polly/test/ScopInfo/int2ptr_ptr2int.ll
M polly/test/ScopInfo/int2ptr_ptr2int_2.ll
Log Message:
-----------
[Polly] Disable vectorization for Polly's fallback loops (#119188)
The patch sets the vectorization metadata to false for Polly's fallback
loops. These are the loops executed when RTCs fail. This minimizes the
multiple loop versioning carried out by Polly and subsequently by the
Loop Vectorizer.
---------
Co-authored-by: Michael Kruse <github at meinersbur.de>
Commit: 0d59fc276190f190ffb065060849af356ddf1359
https://github.com/llvm/llvm-project/commit/0d59fc276190f190ffb065060849af356ddf1359
Author: David Blaikie <dblaikie at gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
R llvm/test/MC/ELF/debug-hash-file-empty-dwarf.s
Log Message:
-----------
Revert "[MC] Fix DWARF file table for files with empty DWARF (#119020)" (#119486)
Reverts llvm/llvm-project#119229
Causes debug info to be unconditionally emitted, regardless of whether
it's requested.
Commit: 10b1caf6b97d8c3ce54b94568cf9a0ca3c564a6f
https://github.com/llvm/llvm-project/commit/10b1caf6b97d8c3ce54b94568cf9a0ca3c564a6f
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRV.h
A llvm/lib/Target/SPIRV/SPIRVPassRegistry.def
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
A llvm/lib/Target/SPIRV/SPIRVStructurizerWrapper.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
Log Message:
-----------
[SPIRV][OPT] Adding flag to run spirv structurizer (#119301)
This PR adds a new flag into OPT to run SPIRV structurizer, this is
being added improving testing of such pass.
This change is required to implement a test request that come
https://github.com/llvm/llvm-project/pull/116331.
---------
Co-authored-by: Joao Saffran <jderezende at microsoft.com>
Commit: bc7449c790bab21d9e09c531ce07607fff5a7688
https://github.com/llvm/llvm-project/commit/bc7449c790bab21d9e09c531ce07607fff5a7688
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
Log Message:
-----------
[RISCV] Adjust vrgather.vv test to avoid disjoint indices. NFC
This is to prevent it from being caught up in the lowering in #119401
Commit: 30ea0f0ce476bf4c12684a9a514af2ca660bbe44
https://github.com/llvm/llvm-project/commit/30ea0f0ce476bf4c12684a9a514af2ca660bbe44
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
Log Message:
-----------
[NFC] [clang] [Serialization] Fix warning for narrowing cast
Commit: 79047fac65b95a5a98bde0de473da858e805576c
https://github.com/llvm/llvm-project/commit/79047fac65b95a5a98bde0de473da858e805576c
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/DomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdaterImpl.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineDomTreeUpdater.h
M llvm/include/llvm/CodeGen/MachineDominators.h
M llvm/include/llvm/CodeGen/MachineSSAContext.h
M llvm/lib/Analysis/DomTreeUpdater.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineDomTreeUpdater.cpp
M llvm/lib/CodeGen/MachineDominanceFrontier.cpp
M llvm/lib/CodeGen/MachineDominators.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLoopInfo.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
M llvm/unittests/Analysis/DomTreeUpdaterTest.cpp
M llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
Log Message:
-----------
[DomTreeUpdater] Move critical edge splitting code to updater (#115111)
Support critical edge splitting in dominator tree updater. Continue the
work in #100856.
Compile time check:
https://llvm-compile-time-tracker.com/compare.php?from=87c35d782795b54911b3e3a91a5b738d4d870e55&to=42b3e5623a9ab4c3648564dc0926b36f3b438a3a&stat=instructions%3Au
Commit: 77b6910b272c254ad7dd96420a7cc41d917b8a9e
https://github.com/llvm/llvm-project/commit/77b6910b272c254ad7dd96420a7cc41d917b8a9e
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
Log Message:
-----------
[Test] Fix the failed test of #108351 (#119495)
Commit: ab15976173e45fd02eb61e922a95ad1f5127c9a0
https://github.com/llvm/llvm-project/commit/ab15976173e45fd02eb61e922a95ad1f5127c9a0
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
A llvm/test/Transforms/Inline/promote-call-bitwidth.ll
Log Message:
-----------
CallPromotionUtils: Correctly use IndexSize when determining the bit width of pointer offsets. (#119483)
This reapplies #119138 with a defensive fix for the assertion failure
when building libcxx.
Unfortunately the failure does not reproduce on my machine, so I am not
able to extract a test case.
The key insight for the fix comes from Jessica Clarke, who observes that
`VTablePtr` may, in fact,
not be a pointer on return from `FindAvailableLoadedValue`.
Co-authored-by: Alexander Richardson <alexander.richardson at cl.cam.ac.uk>
Commit: 3146d57b646c869564669c3e074d6d4fc1ca7500
https://github.com/llvm/llvm-project/commit/3146d57b646c869564669c3e074d6d4fc1ca7500
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86][NFC] Hoist out `N->getOpcode()` used in ReplaceNodeResults (#119494)
Address comment from
https://github.com/llvm/llvm-project/pull/119391/files#r1878388699
Commit: 76b493128cb171455a1890f7bd2b54f32b7ec2a7
https://github.com/llvm/llvm-project/commit/76b493128cb171455a1890f7bd2b54f32b7ec2a7
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/test/tools/llvm-profdata/memprof-yaml.test
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Accept a function name in YAML (#119453)
This patch does two things:
- During deserialization, we accept a function name as an alternative
to the usual GUID represented as a hexadecimal number.
- During serialization, we print a GUID as a 16-digit hexadecimal
number prefixed with 0x in the usual way. (Without this patch, we
print a decimal number, which is not customary.)
In YAML, the MemProf profile is a vector of pairs of GUID and
MemProfRecord. This patch accepts a function name for the GUID, but
it does not accept a function name for the GUID used in Frames yet.
That will be addressed in a subsequent patch.
Commit: acaa5fac499efea7a5d28406c78e4b816941cdf1
https://github.com/llvm/llvm-project/commit/acaa5fac499efea7a5d28406c78e4b816941cdf1
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
Log Message:
-----------
[clang-tidy][NFC] reorder cmake source file (#119374)
Commit: a4538cdcee75b78b7165dda05c9aa7718c4837c4
https://github.com/llvm/llvm-project/commit/a4538cdcee75b78b7165dda05c9aa7718c4837c4
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M libcxxabi/test/forced_unwind2.pass.cpp
Log Message:
-----------
[libc++abi] Don't leak in test (#119505)
Trying to re-enable a test on bots
https://github.com/llvm/llvm-zorg/blob/bb695735dba75e1a5dced13e836f4f46de464bac/zorg/buildbot/builders/sanitizers/buildbot_functions.sh#L443
When we reach `terminate()` `exc` pointer is not
on the stack, so lsan correctly reports a leak.
Commit: ae26f50aea4ef1a6c7058019f0db11a91bbcdade
https://github.com/llvm/llvm-project/commit/ae26f50aea4ef1a6c7058019f0db11a91bbcdade
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
M llvm/test/CodeGen/MIR/Mips/memory-operands.mir
M llvm/test/CodeGen/Mips/2008-06-05-Carry.ll
M llvm/test/CodeGen/Mips/2008-07-03-SRet.ll
M llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll
M llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
M llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
M llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll
M llvm/test/CodeGen/Mips/2008-07-29-icmp.ll
M llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll
M llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll
M llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
M llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll
M llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
M llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll
M llvm/test/CodeGen/Mips/2008-08-07-CC.ll
M llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll
M llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll
M llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
M llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
M llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll
M llvm/test/CodeGen/Mips/2010-11-09-Mul.ll
M llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
M llvm/test/CodeGen/Mips/DbgValueOtherTargets.test
M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
M llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
M llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
M llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
M llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
M llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
M llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
M llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
M llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
M llvm/test/CodeGen/Mips/addc.ll
M llvm/test/CodeGen/Mips/address-selection.ll
M llvm/test/CodeGen/Mips/addressing-mode.ll
M llvm/test/CodeGen/Mips/adjust-callstack-sp.ll
M llvm/test/CodeGen/Mips/alloca.ll
M llvm/test/CodeGen/Mips/alloca16.ll
M llvm/test/CodeGen/Mips/and1.ll
M llvm/test/CodeGen/Mips/ase_warnings.ll
M llvm/test/CodeGen/Mips/asm-large-immediate.ll
M llvm/test/CodeGen/Mips/assertzext-trunc.ll
M llvm/test/CodeGen/Mips/atomic-min-max-64.ll
M llvm/test/CodeGen/Mips/atomic-min-max.ll
M llvm/test/CodeGen/Mips/atomicops.ll
M llvm/test/CodeGen/Mips/biggot.ll
M llvm/test/CodeGen/Mips/brconeq.ll
M llvm/test/CodeGen/Mips/brconeqk.ll
M llvm/test/CodeGen/Mips/brconeqz.ll
M llvm/test/CodeGen/Mips/brconge.ll
M llvm/test/CodeGen/Mips/brcongt.ll
M llvm/test/CodeGen/Mips/brconle.ll
M llvm/test/CodeGen/Mips/brconlt.ll
M llvm/test/CodeGen/Mips/brconne.ll
M llvm/test/CodeGen/Mips/brconnek.ll
M llvm/test/CodeGen/Mips/brconnez.ll
M llvm/test/CodeGen/Mips/brind.ll
M llvm/test/CodeGen/Mips/brundef.ll
M llvm/test/CodeGen/Mips/bswap.ll
M llvm/test/CodeGen/Mips/buildpairextractelementf64.ll
M llvm/test/CodeGen/Mips/call-optimization.ll
M llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved.ll
M llvm/test/CodeGen/Mips/cconv/memory-layout.ll
M llvm/test/CodeGen/Mips/cconv/pr33883.ll
M llvm/test/CodeGen/Mips/cconv/reserved-space.ll
M llvm/test/CodeGen/Mips/cconv/roundl-call.ll
M llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
M llvm/test/CodeGen/Mips/cfi_offset.ll
M llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll
M llvm/test/CodeGen/Mips/check-noat.ll
M llvm/test/CodeGen/Mips/cins.ll
M llvm/test/CodeGen/Mips/cmov.ll
M llvm/test/CodeGen/Mips/cmplarge.ll
M llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
M llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
M llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
M llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll
M llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
M llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
M llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
M llvm/test/CodeGen/Mips/constantfp0.ll
M llvm/test/CodeGen/Mips/constraint-c-err.ll
M llvm/test/CodeGen/Mips/constraint-c.ll
M llvm/test/CodeGen/Mips/constraint-empty.ll
M llvm/test/CodeGen/Mips/countleading.ll
M llvm/test/CodeGen/Mips/cprestore.ll
M llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll
M llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
M llvm/test/CodeGen/Mips/cstmaterialization/stack.ll
M llvm/test/CodeGen/Mips/ctlz-v.ll
M llvm/test/CodeGen/Mips/cttz-v.ll
M llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll
M llvm/test/CodeGen/Mips/delay-slot-kill.ll
M llvm/test/CodeGen/Mips/dext.ll
M llvm/test/CodeGen/Mips/dins.ll
M llvm/test/CodeGen/Mips/disable-tail-merge.ll
M llvm/test/CodeGen/Mips/div.ll
M llvm/test/CodeGen/Mips/div_rem.ll
M llvm/test/CodeGen/Mips/divrem.ll
M llvm/test/CodeGen/Mips/divu.ll
M llvm/test/CodeGen/Mips/divu_remu.ll
M llvm/test/CodeGen/Mips/double2int.ll
M llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
M llvm/test/CodeGen/Mips/dsp-patterns.ll
M llvm/test/CodeGen/Mips/dsp-r1.ll
M llvm/test/CodeGen/Mips/dsp-r2.ll
M llvm/test/CodeGen/Mips/dsp-vec-load-store.ll
M llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
M llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll
M llvm/test/CodeGen/Mips/eh-return32.ll
M llvm/test/CodeGen/Mips/eh-return64.ll
M llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
M llvm/test/CodeGen/Mips/emit-big-cst.ll
M llvm/test/CodeGen/Mips/ex2.ll
M llvm/test/CodeGen/Mips/extins.ll
M llvm/test/CodeGen/Mips/fastcc.ll
M llvm/test/CodeGen/Mips/fcmp.ll
M llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
M llvm/test/CodeGen/Mips/fcopysign.ll
M llvm/test/CodeGen/Mips/fmadd1.ll
M llvm/test/CodeGen/Mips/fp-contract.ll
M llvm/test/CodeGen/Mips/fp-indexed-ls.ll
M llvm/test/CodeGen/Mips/fp-spill-reload.ll
M llvm/test/CodeGen/Mips/fp64a.ll
M llvm/test/CodeGen/Mips/fpbr.ll
M llvm/test/CodeGen/Mips/fpxx.ll
M llvm/test/CodeGen/Mips/frame-address-err.ll
M llvm/test/CodeGen/Mips/frame-address.ll
M llvm/test/CodeGen/Mips/frem.ll
M llvm/test/CodeGen/Mips/global-pointer-reg.ll
M llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll
M llvm/test/CodeGen/Mips/hf16_1.ll
M llvm/test/CodeGen/Mips/i64arg.ll
M llvm/test/CodeGen/Mips/imm.ll
M llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint.ll
M llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
M llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll
M llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
M llvm/test/CodeGen/Mips/ins.ll
M llvm/test/CodeGen/Mips/instverify/dext-pos.mir
M llvm/test/CodeGen/Mips/instverify/dext-size.mir
M llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
M llvm/test/CodeGen/Mips/instverify/dextm-size.mir
M llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
M llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
M llvm/test/CodeGen/Mips/instverify/dextu-size.mir
M llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dins-pos.mir
M llvm/test/CodeGen/Mips/instverify/dins-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
M llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/ext-pos.mir
M llvm/test/CodeGen/Mips/instverify/ext-size.mir
M llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/ins-pos.mir
M llvm/test/CodeGen/Mips/instverify/ins-size.mir
M llvm/test/CodeGen/Mips/int-to-float-conversion.ll
M llvm/test/CodeGen/Mips/internalfunc.ll
M llvm/test/CodeGen/Mips/jumptable_labels.ll
M llvm/test/CodeGen/Mips/largeimm1.ll
M llvm/test/CodeGen/Mips/largeimmprinting.ll
M llvm/test/CodeGen/Mips/lazy-binding.ll
M llvm/test/CodeGen/Mips/lb1.ll
M llvm/test/CodeGen/Mips/lbu1.ll
M llvm/test/CodeGen/Mips/lh1.ll
M llvm/test/CodeGen/Mips/lhu1.ll
M llvm/test/CodeGen/Mips/llcarry.ll
M llvm/test/CodeGen/Mips/llvm-ir/abs.ll
M llvm/test/CodeGen/Mips/llvm-ir/add.ll
M llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
M llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
M llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll
M llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
M llvm/test/CodeGen/Mips/llvm-ir/call.ll
M llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
M llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll
M llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
M llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
M llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll
M llvm/test/CodeGen/Mips/llvm-ir/mul.ll
M llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll
M llvm/test/CodeGen/Mips/llvm-ir/not.ll
M llvm/test/CodeGen/Mips/llvm-ir/ret.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
M llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll
M llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll
M llvm/test/CodeGen/Mips/llvm-ir/sub.ll
M llvm/test/CodeGen/Mips/load-store-left-right.ll
M llvm/test/CodeGen/Mips/long-call-attr.ll
M llvm/test/CodeGen/Mips/long-call-mcount.ll
M llvm/test/CodeGen/Mips/long-calls.ll
M llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
M llvm/test/CodeGen/Mips/machineverifier.ll
M llvm/test/CodeGen/Mips/madd-msub.ll
M llvm/test/CodeGen/Mips/mcount.ll
M llvm/test/CodeGen/Mips/memcpy.ll
M llvm/test/CodeGen/Mips/micromips-addiu.ll
M llvm/test/CodeGen/Mips/micromips-addu16.ll
M llvm/test/CodeGen/Mips/micromips-and16.ll
M llvm/test/CodeGen/Mips/micromips-andi.ll
M llvm/test/CodeGen/Mips/micromips-attr.ll
M llvm/test/CodeGen/Mips/micromips-compact-branches.ll
M llvm/test/CodeGen/Mips/micromips-compact-jump.ll
M llvm/test/CodeGen/Mips/micromips-gp-rc.ll
M llvm/test/CodeGen/Mips/micromips-li.ll
M llvm/test/CodeGen/Mips/micromips-load-effective-address.ll
M llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
M llvm/test/CodeGen/Mips/micromips-not16.ll
M llvm/test/CodeGen/Mips/micromips-or16.ll
M llvm/test/CodeGen/Mips/micromips-shift.ll
M llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll
M llvm/test/CodeGen/Mips/micromips-subu16.ll
M llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll
M llvm/test/CodeGen/Mips/micromips-xor16.ll
M llvm/test/CodeGen/Mips/mips16_32_1.ll
M llvm/test/CodeGen/Mips/mips16fpe.ll
M llvm/test/CodeGen/Mips/mips3-spill-slot.ll
M llvm/test/CodeGen/Mips/mips32r6/compatibility.ll
M llvm/test/CodeGen/Mips/mips64-f128-call.ll
M llvm/test/CodeGen/Mips/mips64-libcall.ll
M llvm/test/CodeGen/Mips/mips64-sret.ll
M llvm/test/CodeGen/Mips/mips64directive.ll
M llvm/test/CodeGen/Mips/mips64ext.ll
M llvm/test/CodeGen/Mips/mips64extins.ll
M llvm/test/CodeGen/Mips/mips64fpimm0.ll
M llvm/test/CodeGen/Mips/mips64fpldst.ll
M llvm/test/CodeGen/Mips/mips64imm.ll
M llvm/test/CodeGen/Mips/mips64instrs.ll
M llvm/test/CodeGen/Mips/mips64intldst.ll
M llvm/test/CodeGen/Mips/mips64lea.ll
M llvm/test/CodeGen/Mips/mips64muldiv.ll
M llvm/test/CodeGen/Mips/mips64r6/compatibility.ll
M llvm/test/CodeGen/Mips/mips64shift.ll
M llvm/test/CodeGen/Mips/mips64signextendsesf.ll
M llvm/test/CodeGen/Mips/mips64sinttofpsf.ll
M llvm/test/CodeGen/Mips/mipslopat.ll
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
M llvm/test/CodeGen/Mips/misha.ll
M llvm/test/CodeGen/Mips/msa/2r.ll
M llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
M llvm/test/CodeGen/Mips/msa/2rf.ll
M llvm/test/CodeGen/Mips/msa/2rf_exup.ll
M llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/2rf_fq.ll
M llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/2rf_tq.ll
M llvm/test/CodeGen/Mips/msa/3r-a.ll
M llvm/test/CodeGen/Mips/msa/3r-b.ll
M llvm/test/CodeGen/Mips/msa/3r-c.ll
M llvm/test/CodeGen/Mips/msa/3r-d.ll
M llvm/test/CodeGen/Mips/msa/3r-i.ll
M llvm/test/CodeGen/Mips/msa/3r-m.ll
M llvm/test/CodeGen/Mips/msa/3r-p.ll
M llvm/test/CodeGen/Mips/msa/3r-s.ll
M llvm/test/CodeGen/Mips/msa/3r-v.ll
M llvm/test/CodeGen/Mips/msa/3r_4r.ll
M llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
M llvm/test/CodeGen/Mips/msa/3r_splat.ll
M llvm/test/CodeGen/Mips/msa/3rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
M llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
M llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/3rf_q.ll
M llvm/test/CodeGen/Mips/msa/arithmetic.ll
M llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
M llvm/test/CodeGen/Mips/msa/basic_operations.ll
M llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
M llvm/test/CodeGen/Mips/msa/bit.ll
M llvm/test/CodeGen/Mips/msa/bitcast.ll
M llvm/test/CodeGen/Mips/msa/bitwise.ll
M llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
M llvm/test/CodeGen/Mips/msa/compare.ll
M llvm/test/CodeGen/Mips/msa/compare_float.ll
M llvm/test/CodeGen/Mips/msa/elm_copy.ll
M llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
M llvm/test/CodeGen/Mips/msa/elm_insv.ll
M llvm/test/CodeGen/Mips/msa/elm_move.ll
M llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
M llvm/test/CodeGen/Mips/msa/emergency-spill.mir
M llvm/test/CodeGen/Mips/msa/endian.ll
M llvm/test/CodeGen/Mips/msa/fexuprl.ll
M llvm/test/CodeGen/Mips/msa/frameindex.ll
M llvm/test/CodeGen/Mips/msa/i10.ll
M llvm/test/CodeGen/Mips/msa/i5-a.ll
M llvm/test/CodeGen/Mips/msa/i5-b.ll
M llvm/test/CodeGen/Mips/msa/i5-c.ll
M llvm/test/CodeGen/Mips/msa/i5-m.ll
M llvm/test/CodeGen/Mips/msa/i5-s.ll
M llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
M llvm/test/CodeGen/Mips/msa/i8.ll
M llvm/test/CodeGen/Mips/msa/immediates-bad.ll
M llvm/test/CodeGen/Mips/msa/immediates.ll
M llvm/test/CodeGen/Mips/msa/inline-asm.ll
M llvm/test/CodeGen/Mips/msa/ldr_str.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
M llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll
M llvm/test/CodeGen/Mips/msa/nori.b.ll
M llvm/test/CodeGen/Mips/msa/remat-ldi.ll
M llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
M llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
M llvm/test/CodeGen/Mips/msa/shift_no_and.ll
M llvm/test/CodeGen/Mips/msa/shuffle.ll
M llvm/test/CodeGen/Mips/msa/special.ll
M llvm/test/CodeGen/Mips/msa/spill.ll
M llvm/test/CodeGen/Mips/msa/vec.ll
M llvm/test/CodeGen/Mips/msa/vecs10.ll
M llvm/test/CodeGen/Mips/mul.ll
M llvm/test/CodeGen/Mips/mulll.ll
M llvm/test/CodeGen/Mips/mulull.ll
M llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
M llvm/test/CodeGen/Mips/neg1.ll
M llvm/test/CodeGen/Mips/nmadd.ll
M llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll
M llvm/test/CodeGen/Mips/not1.ll
M llvm/test/CodeGen/Mips/null.ll
M llvm/test/CodeGen/Mips/o32_cc.ll
M llvm/test/CodeGen/Mips/o32_cc_vararg.ll
M llvm/test/CodeGen/Mips/octeon.ll
M llvm/test/CodeGen/Mips/octeon_popcnt.ll
M llvm/test/CodeGen/Mips/optimize-fp-math.ll
M llvm/test/CodeGen/Mips/or1.ll
M llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
M llvm/test/CodeGen/Mips/pr33682.ll
M llvm/test/CodeGen/Mips/pr33978.ll
M llvm/test/CodeGen/Mips/prevent-hoisting.ll
M llvm/test/CodeGen/Mips/private.ll
M llvm/test/CodeGen/Mips/ra-allocatable.ll
M llvm/test/CodeGen/Mips/rem.ll
M llvm/test/CodeGen/Mips/remat-immed-load.ll
M llvm/test/CodeGen/Mips/remu.ll
M llvm/test/CodeGen/Mips/return-vector.ll
M llvm/test/CodeGen/Mips/return_address.ll
M llvm/test/CodeGen/Mips/return_address_err.ll
M llvm/test/CodeGen/Mips/rotate.ll
M llvm/test/CodeGen/Mips/sb1.ll
M llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezSlti.ll
M llvm/test/CodeGen/Mips/selectcc.ll
M llvm/test/CodeGen/Mips/selectiondag-optlevel.ll
M llvm/test/CodeGen/Mips/seleq.ll
M llvm/test/CodeGen/Mips/seleqk.ll
M llvm/test/CodeGen/Mips/selgek.ll
M llvm/test/CodeGen/Mips/selgt.ll
M llvm/test/CodeGen/Mips/selle.ll
M llvm/test/CodeGen/Mips/selltk.ll
M llvm/test/CodeGen/Mips/selne.ll
M llvm/test/CodeGen/Mips/selnek.ll
M llvm/test/CodeGen/Mips/selpat.ll
M llvm/test/CodeGen/Mips/setcc-se.ll
M llvm/test/CodeGen/Mips/seteq.ll
M llvm/test/CodeGen/Mips/seteqz.ll
M llvm/test/CodeGen/Mips/setge.ll
M llvm/test/CodeGen/Mips/setgek.ll
M llvm/test/CodeGen/Mips/setle.ll
M llvm/test/CodeGen/Mips/setlt.ll
M llvm/test/CodeGen/Mips/setltk.ll
M llvm/test/CodeGen/Mips/setne.ll
M llvm/test/CodeGen/Mips/setuge.ll
M llvm/test/CodeGen/Mips/setugt.ll
M llvm/test/CodeGen/Mips/setule.ll
M llvm/test/CodeGen/Mips/setult.ll
M llvm/test/CodeGen/Mips/setultk.ll
M llvm/test/CodeGen/Mips/sh1.ll
M llvm/test/CodeGen/Mips/shift-parts.ll
M llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
M llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll
M llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
M llvm/test/CodeGen/Mips/sll1.ll
M llvm/test/CodeGen/Mips/sll2.ll
M llvm/test/CodeGen/Mips/slt.ll
M llvm/test/CodeGen/Mips/spill-copy-acreg.ll
M llvm/test/CodeGen/Mips/sra1.ll
M llvm/test/CodeGen/Mips/sra2.ll
M llvm/test/CodeGen/Mips/srl1.ll
M llvm/test/CodeGen/Mips/srl2.ll
M llvm/test/CodeGen/Mips/stack-alignment.ll
M llvm/test/CodeGen/Mips/stackcoloring.ll
M llvm/test/CodeGen/Mips/stchar.ll
M llvm/test/CodeGen/Mips/stldst.ll
M llvm/test/CodeGen/Mips/sub1.ll
M llvm/test/CodeGen/Mips/sub2.ll
M llvm/test/CodeGen/Mips/swzero.ll
M llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll
M llvm/test/CodeGen/Mips/thread-pointer.ll
M llvm/test/CodeGen/Mips/tls-alias.ll
M llvm/test/CodeGen/Mips/tnaked.ll
M llvm/test/CodeGen/Mips/trap.ll
M llvm/test/CodeGen/Mips/uitofp.ll
M llvm/test/CodeGen/Mips/ul1.ll
M llvm/test/CodeGen/Mips/unaligned-memops.ll
M llvm/test/CodeGen/Mips/unalignedload.ll
M llvm/test/CodeGen/Mips/vector-load-store.ll
M llvm/test/CodeGen/Mips/vector-setcc.ll
M llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
M llvm/test/CodeGen/Mips/vr4300-mulmul.ll
M llvm/test/CodeGen/Mips/weak.ll
M llvm/test/CodeGen/Mips/whitespace.ll
M llvm/test/CodeGen/Mips/xor1.ll
M llvm/test/CodeGen/Mips/zeroreg.ll
M llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
M llvm/test/DebugInfo/Mips/tls.ll
Log Message:
-----------
[test] Change llc -march=mips* to -mtriple=mips*
Similar to 806761a7629df268c8aed49657aeccffa6bca449
Commit: d78fe84d49b3db675ae4c502ead38ce9e5c2539f
https://github.com/llvm/llvm-project/commit/d78fe84d49b3db675ae4c502ead38ce9e5c2539f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)
Commit: 5797ed660ab0c1847bd6229af262f841b2f753ae
https://github.com/llvm/llvm-project/commit/5797ed660ab0c1847bd6229af262f841b2f753ae
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Log Message:
-----------
[GISel][SDAG] Avoid push_back in loops for some shuffle mask handling. (#119434)
Each call to push_back contains a check to see if the vector needs to
grow. Using resize or giving the size to the constructor can reduce
the number of checks for growing.
Commit: 839c8217b989a22908fdd1ec48105ff22d655fb2
https://github.com/llvm/llvm-project/commit/839c8217b989a22908fdd1ec48105ff22d655fb2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/X86/bfloat.ll
Log Message:
-----------
[LegalizeTypes][RISCV][X86] Legalize FP_ROUND to libcall in SoftPromoteHalfRes_FP_ROUND if the input type is softened. (#119481)
Previously we created an FP_TO_FP16 and legalized it in
SoftenFloatOp_FP_ROUND. This caused i16 to be sent to call lowering
instead of f16. This results in the ABI not being followed if f16 is
supposed to be passed in a different register than i16.
Looking at the libgcc binary for the library function it appears the value
is returned in xmm0 so the X86 test was being miscompiled before.
Fixes #107607.
Commit: 553058f825157b33a2d7f793c811f301260b765b
https://github.com/llvm/llvm-project/commit/553058f825157b33a2d7f793c811f301260b765b
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/DomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdaterImpl.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineDomTreeUpdater.h
M llvm/include/llvm/CodeGen/MachineDominators.h
M llvm/include/llvm/CodeGen/MachineSSAContext.h
M llvm/lib/Analysis/DomTreeUpdater.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineDomTreeUpdater.cpp
M llvm/lib/CodeGen/MachineDominanceFrontier.cpp
M llvm/lib/CodeGen/MachineDominators.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLoopInfo.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
M llvm/unittests/Analysis/DomTreeUpdaterTest.cpp
M llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
Log Message:
-----------
Revert "[DomTreeUpdater] Move critical edge splitting code to updater" (#119512)
Reverts llvm/llvm-project#115111 Causes #119511
Commit: 2f18b5ef030e37f3b229e767081a804b7c038a07
https://github.com/llvm/llvm-project/commit/2f18b5ef030e37f3b229e767081a804b7c038a07
Author: David Green <david.green at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/cast.ll
M llvm/test/Analysis/CostModel/AArch64/sve-cast.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/predicated-reduction.ll
Log Message:
-----------
[AArch64] Add fpext and fpround costs (#119292)
This adds some basic costs for fpext and fpround, many of which were
already handled by the generic costing routines but this does make some
adjustments for larger vector types that can use fcvtn+fcvtn2, as
opposed to fcvtn+fcvtn+concat.
These should now more closely match the codegen from
https://godbolt.org/z/r3P9Mf8ez, for example.
Commit: c38a0de6915592cf488965a995d8aa6e7783adcd
https://github.com/llvm/llvm-project/commit/c38a0de6915592cf488965a995d8aa6e7783adcd
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][nfc] Update vectorize-tensor-extract.mlir (1/N) (#118977)
Tests in "vectorize-tensor-extract.mlir" are inconsistent and would
benefit from refactoring to:
* Clearly categorize tests into "contiguous load," "gather load," and
"scalar load + broadcast" cases, reflecting the structure of
tensor.extract vectorization.
* Unify variable naming (both MLIR and FileCheck).
* Ensure all tests exercise unmasked vectorization (masked vectorization
is covered in "vectorize-tensor-extract-masked.mlir").
* Improve and standardize formatting.
These changes will make it easier to identify the test cases being
exercised and simplify future maintenance or refactoring.
This is patch 1/N in the series; below is a summary of the specific
changes
in this patch.
----------------------------------------------------------------------
Summary for patch 1/N
----------------------------------------------------------------------
This PR updates the `@vectorize_scalar_broadcast_column_tensor` test in
"vectorize-tensor-extract.mlir", which exercises:
* Vectorization of tensor.extract.
* A scalar read followed by a broadcast.
* Reading from a constant column tensor.
Currently, the test uses "masked" vectorization, but the file
exclusively tests unmasked vectorization paths. To address this
inconsistency, this PR removes masking, aligning the test with the rest
of the file. Masked vectorization scenarios remain covered in
"vectorize-tensor-extract-masked.mlir". This update switches from:
* `transform.structured.vectorize`, to
* `transform.structured.vectorize_children_and_apply_patterns`.
The latter approach applies canonicalization patterns, significantly
simplifying the generated output.
Additional improvements for readability:
* Renamed the test function for clarity.
* Updated variable names and removed unused variables.
* Added empty lines for better formatting.
Commit: be06c79c4591a64bbd6b50cb711b450712b04d9c
https://github.com/llvm/llvm-project/commit/be06c79c4591a64bbd6b50cb711b450712b04d9c
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][linalg] Enable Vectorization of 0-D tensor.extract (#119079)
This patch removes an assert in `vectorizeTensorExtract` that was
blocking
the vectorization of 0-D tensor.extract operations, e.g.:
```mlir
%1 = tensor.extract %src[] : tensor<f32>
```
As demonstrated by the included tests, this case is already effectively
supported.
**Context**
The removed assert was introduced in #109580 as a guard, pending proper
support
and testing for 0-D tensors. This PR addresses that previously
undocumented
TODO. Apologies for the oversight!
**Updates and Tests**
* Revised the existing test `@negative_no_loop` to ensure the
`vectorize_nd_extract` attribute is included, allowing the vectorizer
to process it. The test was renamed and variables updated for clarity.
* Added a new test `@extract_scalar_from_0d_into_1d` to cover "mixed"
0-D/1-D tensor extraction, e.g.:
```mlir
%res = linalg.generic {
indexing_maps = [#map],
iterator_types = ["parallel"]
} outs(%init : tensor<1xf32>) {
^bb0(%in: f32):
%1 = tensor.extract %src[] : tensor<f32>
linalg.yield %1 : f32
} -> tensor<1xf32>
return %res : tensor<1xf32>
```
**Additional updates**
I also took the liberty and improved test coverage for 0-D tensor in the
vectorizer tests:
* Added a specific test for "0D linalg.generic" in
"vectorization-with-patterns.mlir".
* Renamed several tests in "vectorization-with-patterns.mlir" to clarify
that the 0-D case is now covered.
Commit: 2fe30bc6693c60d76c7e44d9fd6323c39125c19e
https://github.com/llvm/llvm-project/commit/2fe30bc6693c60d76c7e44d9fd6323c39125c19e
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
Log Message:
-----------
[AArch64] Add cost model for @experimental.vector.match (#118512)
The base cost approximates the expansion code in SelectionDAGBuilder.
For the AArch64 cases that don't need generic expansion, fixed-length
search vectors have a higher cost than scalable vectors due to the extra
instructions to convert the boolean mask.
Commit: 884f2ad6f9e269407366622ac80e65a1bb1b4b2e
https://github.com/llvm/llvm-project/commit/884f2ad6f9e269407366622ac80e65a1bb1b4b2e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/LLVMContext.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
Log Message:
-----------
DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm (#119485)
Currently LLVMContext::emitError emits any error as an "inline asm"
error which does not make any sense. InlineAsm appears to be special,
in that it uses a "LocCookie" from srcloc metadata, which looks like
a parallel mechanism to ordinary source line locations. This meant
that other types of failures had degraded source information reported
when available.
Introduce some new generic error types, and only use inline asm
in the appropriate contexts. The DiagnosticInfo types are still
a bit of a mess, and I'm not sure why DiagnosticInfoWithLocationBase
exists instead of just having an optional DiagnosticLocation in the
base class.
DK_Generic is for any error that derives from an IR level instruction,
and thus can pull debug locations directly from it. DK_GenericWithLoc
is functionally the generic codegen error, since it does not depend
on the IR and instead can construct a DiagnosticLocation from the
MI debug location.
Commit: 1bc1703eb5bace50d69158bc6a77ac31ff36be77
https://github.com/llvm/llvm-project/commit/1bc1703eb5bace50d69158bc6a77ac31ff36be77
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/IR/DiagnosticPrinter.cpp
Log Message:
-----------
DiagnosticPrinter: Use printAsOperand to handle anonymous values (#119491)
To avoid changing the behavior in the general case, only do this
for anonymous functions. Otherwise, we'll end up with a leading
'@' on the name, which may not be meaningful to end users.
Commit: 796a1cf70639697325a86a56a0e482add19e1d56
https://github.com/llvm/llvm-project/commit/796a1cf70639697325a86a56a0e482add19e1d56
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
A mlir/test/Dialect/Linalg/td/vectorize-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][nfc] Update vectorize-tensor-extract.mlir (2/N) (#119080)
Tests in "vectorize-tensor-extract.mlir" are inconsistent and would
benefit from refactoring to:
* Clearly categorize tests into "contiguous load," "gather load," and
"scalar load + broadcast" cases, reflecting the structure of
tensor.extract vectorization.
* Unify variable naming (both MLIR and FileCheck).
* Ensure all tests exercise unmasked vectorization (masked vectorization
is covered in "vectorize-tensor-extract-masked.mlir").
* Improve and standardize formatting.
These changes will make it easier to identify the test cases being
exercised and simplify future maintenance or refactoring.
This is patch 2/N in the series; below is a summary of the specific
changes
in this patch.
----------------------------------------------------------------------
Summary of patch 2/N
----------------------------------------------------------------------
Makes all tests re-use the same TD sequence. This TD sequence has been
extracted to a deducted file:
* "td/vectorize-with-patterns.mlir".
----------------------------------------------------------------------
Previous patches:
----------------------------------------------------------------------
* https://github.com/llvm/llvm-project/pull/118977
Commit: 74393f3da0c84ac40596ae561269a2bddf72504e
https://github.com/llvm/llvm-project/commit/74393f3da0c84ac40596ae561269a2bddf72504e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
Log Message:
-----------
[clang][bytecode][NFC] Avoid calling ASTContext::getTypeSize() (#119392)
In the case of primitive arrays, we can do this once and reuse the value
for all elements.
Commit: 9cdb7d2b6c333874ec969ef6ac64e0354bb3aa91
https://github.com/llvm/llvm-project/commit/9cdb7d2b6c333874ec969ef6ac64e0354bb3aa91
Author: Sven van Haastregt <sven.vanhaastregt at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/Maintainers.rst
Log Message:
-----------
[NFC] Maintainers.rst: align email address formatting
Follow the formatting for other email addresses in this file.
Commit: b0763a472be6098e8c8bdb32c06c593750e0566e
https://github.com/llvm/llvm-project/commit/b0763a472be6098e8c8bdb32c06c593750e0566e
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_cvt.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
Log Message:
-----------
[AArch64] Implement intrinsics for FP8 FCVT/FCVTN/BFCVT (#118025)
This patch implements the following intrinsics:
Convert to packed 8-bit floating-point format.
``` c
// Variants are also available for: _mf8[_bf16_x2] and _mf8[_f32_x4]
svmfloat8_t svcvt_mf8[_f16_x2]_fpm(svfloat16x2_t zn, fpm_t fpm) __arm_streaming;
```
Convert to interleaved 8-bit floating-point format.
``` c
svmfloat8_t svcvtn_mf8[_f32_x4]_fpm(svfloat32x4_t zn, fpm_t fpm) __arm_streaming;
```
In accordance with https://github.com/ARM-software/acle/pull/323.
Co-authored-by: Marin Lukac marian.lukac at arm.com
Co-authored-by: Caroline Concatto caroline.concatto at arm.com
Commit: 2dc22615fd46ab2566d0f26d5ba234ab12dc4bf8
https://github.com/llvm/llvm-project/commit/2dc22615fd46ab2566d0f26d5ba234ab12dc4bf8
Author: David Justo <david.justo.1996 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M compiler-rt/lib/asan/asan_flags.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
A compiler-rt/test/asan/TestCases/Windows/allocator_may_return_null_limits.cpp
Log Message:
-----------
[ASan] Honor `allocator_may_return_null` when set through user-function and fix large alloc edge case (#117929)
**Related:** #117925
**About this PR:**
This PR performs 3 small but related fixes for ASan users on Windows:
1. It ensures that the `allocator_may_return_null` flag is honored when
set through the user function `__asan_default_options`. For more
details, please see: #117925
2. It adds a missing `AllocatorMayReturnNull()` check inside
`InternalAlloc` that's needed to avoid error'ing out when the allocator
_correctly_ returns `null` when `allocator_may_return_null` is set.
3. In `sanitizer_win`'s `ReturnNullptrOnOOMOrDie`, it allows returning
`null` when the last error is set to `ERROR_INVALID_PARAMETER` which may
be set by `VirtualAlloc` on WIndows when attempting to allocate
exceedingly large memory.
I've added test cases that should cover these new behaviors. Happy to
take on any feedback as well. Thank you :-)
---------
Co-authored-by: David Justo <dajusto at microsoft.com>
Commit: a1ee1a9126678aabd3b02ef1367df8879d2536fa
https://github.com/llvm/llvm-project/commit/a1ee1a9126678aabd3b02ef1367df8879d2536fa
Author: Guillaume DI FATTA <124087040+Atafid at users.noreply.github.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/docs/StackMaps.rst
M llvm/include/llvm/IR/Intrinsics.td
A llvm/test/CodeGen/AArch64/stackmap-args.ll
A llvm/test/CodeGen/PowerPC/ppc64-stackmap-args.ll
A llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
A llvm/test/CodeGen/SystemZ/stackmap-args.ll
A llvm/test/CodeGen/X86/stackmap-args.ll
Log Message:
-----------
[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)
This pull request modifies the behavior of the
`@llvm.experimental.stackmap` intrinsic to require that its two first
operands (`id` and `numShadowBytes`) be **immediate values**. This
change ensures that variables cannot be passed as two first arguments to
this intrinsic.
Related Issue: https://github.com/llvm/llvm-project/issues/115733
### Testing
- Added new test cases to ensure errors are emitted for non-immediate
operands.
- Ran the full LLVM test suite to verify no regressions were introduced.
Commit: 71fd5288d28169cc4a6ae0bcf6c19a8130368936
https://github.com/llvm/llvm-project/commit/71fd5288d28169cc4a6ae0bcf6c19a8130368936
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M .ci/generate_test_report.py
Log Message:
-----------
[ci] Include a log download link when test report is truncated (#117985)
Now "Download" will be a link to the file so people don't have to know
to open the build tab and find the download button.
This is a URL from a real build:
https://buildkite.com/organizations/llvm-project/pipelines/github-pull-requests/builds/123979/jobs/01937132-0fc3-4c95-a884-2fc0048cb9a7/download.txt
And this is how we can build it:
https://buildkite.com/organizations/{BUILDKITE_ORGANIZATION_SLUG}/pipelines/{BUILDKITE_PIPELINE_SLUG}/builds/{BUILDKITE_BUILD_NUMBER}/jobs/{BUILDKITE_JOB_ID}/download.txt
Given these env vars that were set in that job:
BUILDKITE_ORGANIZATION_SLUG="llvm-project"
BUILDKITE_PIPELINE_SLUG="github-pull-requests"
BUILDKITE_BUILD_NUMBER="123979"
BUILDKITE_JOB_ID="01937132-0fc3-4c95-a884-2fc0048cb9a7"
In theory these will always be available but:
1. Rather safe than sorry with this script, I don't want to make a
passing
build a failure because this script failed.
2. It would get very annoying if you had to set all these to test
the script locally.
Commit: 8d714db7f9617252401f85537d672c5b92c20557
https://github.com/llvm/llvm-project/commit/8d714db7f9617252401f85537d672c5b92c20557
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang-tools-extra/clangd/refactor/tweaks/ExtractVariable.cpp
M clang-tools-extra/clangd/unittests/tweaks/ExtractVariableTests.cpp
Log Message:
-----------
[clangd] Consider expression statements in ExtractVariable tweak (#112525)
For instance:
int func();
int main()
{
func(); // => auto placeholder = func();
}
Commit: 14dcf8214f9c66172d17c1cfaec6aec0030748e0
https://github.com/llvm/llvm-project/commit/14dcf8214f9c66172d17c1cfaec6aec0030748e0
Author: Peter Waller <peter.waller at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
A bolt/test/AArch64/pad-before-funcs.s
Log Message:
-----------
[BOLT] Add --pad-funcs-before=func:n (#117924)
This complements --pad-funcs, and by using both simultaneously, enables
moving a specific function through the address space without modifying
any code
other than the targeted function (and references to it) by doing
(before+after=constant).
See also: proposed functionality to enable inserting random padding in
https://discourse.llvm.org/t/rfc-lld-feature-for-controlling-for-code-size-dependent-measurement-bias
and https://github.com/llvm/llvm-project/pull/117653
Commit: 4dde52d76b5342fd7e0b51094580818f3934ae2f
https://github.com/llvm/llvm-project/commit/4dde52d76b5342fd7e0b51094580818f3934ae2f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Check for overlapping memcpy regions (#119535)
Commit: 088e74cf73549b556cb718f5322ae40a2c84a1f8
https://github.com/llvm/llvm-project/commit/088e74cf73549b556cb718f5322ae40a2c84a1f8
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/test/tools/llvm-readobj/ELF/note-core.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[llvm][llvm-readobj] Add NT_ARM_GCS Linux core note type (#117545)
The ARM Guarded Control Stack extension (GCS) is similar to existing
shadow stack extensions for other architectures.
The core note will include which features of GCS are enabled, which have
been locked in their current state, and the stack pointer of the shadow
stack.
Note that 0x40f is NT_ARM_POE, FPMR is supported by LLDB and GCS will be
soon, POE is not at this time. So NT_ARM_POE will be added when that
work starts.
See
https://github.com/torvalds/linux/blob/master/include/uapi/linux/elf.h.
Commit: ca1d9d6a2c88fc262a1857aa95b9b9099a9276f0
https://github.com/llvm/llvm-project/commit/ca1d9d6a2c88fc262a1857aa95b9b9099a9276f0
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M .ci/generate_test_report.py
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
A bolt/test/AArch64/pad-before-funcs.s
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
M clang-tools-extra/clangd/refactor/tweaks/ExtractVariable.cpp
M clang-tools-extra/clangd/unittests/tweaks/ExtractVariableTests.cpp
M clang/Maintainers.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExternalASTSource.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExternalASTSource.cpp
M clang/lib/AST/ODRHash.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Serialization/ASTCommon.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderInternals.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/CMakeLists.txt
A clang/lib/Serialization/TemplateArgumentHasher.cpp
A clang/lib/Serialization/TemplateArgumentHasher.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/test/CodeGen/ubsan-trap-merge.c
M clang/test/CodeGenCXX/catch-undef-behavior.cpp
M clang/test/Modules/cxx-templates.cpp
M clang/test/Modules/odr_hash.cpp
A clang/test/Modules/recursive-instantiations.cppm
M clang/test/OpenMP/target_parallel_ast_print.cpp
M clang/test/OpenMP/target_teams_ast_print.cpp
M clang/test/OpenMP/task_ast_print.cpp
M clang/test/OpenMP/teams_ast_print.cpp
M clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Serialization/CMakeLists.txt
A clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/asan/asan_flags.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
M compiler-rt/lib/scudo/standalone/list.h
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_interface.cpp
A compiler-rt/lib/xray/xray_riscv.cpp
A compiler-rt/lib/xray/xray_trampoline_riscv32.S
A compiler-rt/lib/xray/xray_trampoline_riscv64.S
A compiler-rt/lib/xray/xray_trampoline_riscv_common.S
M compiler-rt/lib/xray/xray_tsc.h
A compiler-rt/test/asan/TestCases/Windows/allocator_may_return_null_limits.cpp
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
M libcxxabi/src/demangle/ItaniumDemangle.h
M libcxxabi/test/forced_unwind2.pass.cpp
M libcxxabi/test/test_demangle.pass.cpp
M lld/ELF/OutputSections.cpp
M lld/test/ELF/linkerscript/section-class.test
M lldb/source/DataFormatters/FormatterBytecode.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h
M llvm/docs/StackMaps.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/Demangle/ItaniumDemangle.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/DiagnosticPrinter.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRV.h
A llvm/lib/Target/SPIRV/SPIRVPassRegistry.def
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
A llvm/lib/Target/SPIRV/SPIRVStructurizerWrapper.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/XRay/InstrumentationMap.cpp
M llvm/test/Analysis/CostModel/AArch64/cast.ll
M llvm/test/Analysis/CostModel/AArch64/sve-cast.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
A llvm/test/CodeGen/AArch64/stackmap-args.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
M llvm/test/CodeGen/MIR/Mips/memory-operands.mir
M llvm/test/CodeGen/Mips/2008-06-05-Carry.ll
M llvm/test/CodeGen/Mips/2008-07-03-SRet.ll
M llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll
M llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
M llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
M llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll
M llvm/test/CodeGen/Mips/2008-07-29-icmp.ll
M llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll
M llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll
M llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
M llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll
M llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
M llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll
M llvm/test/CodeGen/Mips/2008-08-07-CC.ll
M llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll
M llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll
M llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
M llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
M llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll
M llvm/test/CodeGen/Mips/2010-11-09-Mul.ll
M llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
M llvm/test/CodeGen/Mips/DbgValueOtherTargets.test
M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
M llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
M llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
M llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
M llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
M llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
M llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
M llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
M llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
M llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
M llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
M llvm/test/CodeGen/Mips/addc.ll
M llvm/test/CodeGen/Mips/address-selection.ll
M llvm/test/CodeGen/Mips/addressing-mode.ll
M llvm/test/CodeGen/Mips/adjust-callstack-sp.ll
M llvm/test/CodeGen/Mips/alloca.ll
M llvm/test/CodeGen/Mips/alloca16.ll
M llvm/test/CodeGen/Mips/and1.ll
M llvm/test/CodeGen/Mips/ase_warnings.ll
M llvm/test/CodeGen/Mips/asm-large-immediate.ll
M llvm/test/CodeGen/Mips/assertzext-trunc.ll
M llvm/test/CodeGen/Mips/atomic-min-max-64.ll
M llvm/test/CodeGen/Mips/atomic-min-max.ll
M llvm/test/CodeGen/Mips/atomicops.ll
M llvm/test/CodeGen/Mips/biggot.ll
M llvm/test/CodeGen/Mips/brconeq.ll
M llvm/test/CodeGen/Mips/brconeqk.ll
M llvm/test/CodeGen/Mips/brconeqz.ll
M llvm/test/CodeGen/Mips/brconge.ll
M llvm/test/CodeGen/Mips/brcongt.ll
M llvm/test/CodeGen/Mips/brconle.ll
M llvm/test/CodeGen/Mips/brconlt.ll
M llvm/test/CodeGen/Mips/brconne.ll
M llvm/test/CodeGen/Mips/brconnek.ll
M llvm/test/CodeGen/Mips/brconnez.ll
M llvm/test/CodeGen/Mips/brind.ll
M llvm/test/CodeGen/Mips/brundef.ll
M llvm/test/CodeGen/Mips/bswap.ll
M llvm/test/CodeGen/Mips/buildpairextractelementf64.ll
M llvm/test/CodeGen/Mips/call-optimization.ll
M llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved.ll
M llvm/test/CodeGen/Mips/cconv/memory-layout.ll
M llvm/test/CodeGen/Mips/cconv/pr33883.ll
M llvm/test/CodeGen/Mips/cconv/reserved-space.ll
M llvm/test/CodeGen/Mips/cconv/roundl-call.ll
M llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
M llvm/test/CodeGen/Mips/cfi_offset.ll
M llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll
M llvm/test/CodeGen/Mips/check-noat.ll
M llvm/test/CodeGen/Mips/cins.ll
M llvm/test/CodeGen/Mips/cmov.ll
M llvm/test/CodeGen/Mips/cmplarge.ll
M llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
M llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
M llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
M llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll
M llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
M llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
M llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
M llvm/test/CodeGen/Mips/constantfp0.ll
M llvm/test/CodeGen/Mips/constraint-c-err.ll
M llvm/test/CodeGen/Mips/constraint-c.ll
M llvm/test/CodeGen/Mips/constraint-empty.ll
M llvm/test/CodeGen/Mips/countleading.ll
M llvm/test/CodeGen/Mips/cprestore.ll
M llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll
M llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
M llvm/test/CodeGen/Mips/cstmaterialization/stack.ll
M llvm/test/CodeGen/Mips/ctlz-v.ll
M llvm/test/CodeGen/Mips/cttz-v.ll
M llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll
M llvm/test/CodeGen/Mips/delay-slot-kill.ll
M llvm/test/CodeGen/Mips/dext.ll
M llvm/test/CodeGen/Mips/dins.ll
M llvm/test/CodeGen/Mips/disable-tail-merge.ll
M llvm/test/CodeGen/Mips/div.ll
M llvm/test/CodeGen/Mips/div_rem.ll
M llvm/test/CodeGen/Mips/divrem.ll
M llvm/test/CodeGen/Mips/divu.ll
M llvm/test/CodeGen/Mips/divu_remu.ll
M llvm/test/CodeGen/Mips/double2int.ll
M llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
M llvm/test/CodeGen/Mips/dsp-patterns.ll
M llvm/test/CodeGen/Mips/dsp-r1.ll
M llvm/test/CodeGen/Mips/dsp-r2.ll
M llvm/test/CodeGen/Mips/dsp-vec-load-store.ll
M llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
M llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll
M llvm/test/CodeGen/Mips/eh-return32.ll
M llvm/test/CodeGen/Mips/eh-return64.ll
M llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
M llvm/test/CodeGen/Mips/emit-big-cst.ll
M llvm/test/CodeGen/Mips/ex2.ll
M llvm/test/CodeGen/Mips/extins.ll
M llvm/test/CodeGen/Mips/fastcc.ll
M llvm/test/CodeGen/Mips/fcmp.ll
M llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
M llvm/test/CodeGen/Mips/fcopysign.ll
M llvm/test/CodeGen/Mips/fmadd1.ll
M llvm/test/CodeGen/Mips/fp-contract.ll
M llvm/test/CodeGen/Mips/fp-indexed-ls.ll
M llvm/test/CodeGen/Mips/fp-spill-reload.ll
M llvm/test/CodeGen/Mips/fp64a.ll
M llvm/test/CodeGen/Mips/fpbr.ll
M llvm/test/CodeGen/Mips/fpxx.ll
M llvm/test/CodeGen/Mips/frame-address-err.ll
M llvm/test/CodeGen/Mips/frame-address.ll
M llvm/test/CodeGen/Mips/frem.ll
M llvm/test/CodeGen/Mips/global-pointer-reg.ll
M llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll
M llvm/test/CodeGen/Mips/hf16_1.ll
M llvm/test/CodeGen/Mips/i64arg.ll
M llvm/test/CodeGen/Mips/imm.ll
M llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
M llvm/test/CodeGen/Mips/inlineasm-constraint.ll
M llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
M llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll
M llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
M llvm/test/CodeGen/Mips/ins.ll
M llvm/test/CodeGen/Mips/instverify/dext-pos.mir
M llvm/test/CodeGen/Mips/instverify/dext-size.mir
M llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
M llvm/test/CodeGen/Mips/instverify/dextm-size.mir
M llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
M llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
M llvm/test/CodeGen/Mips/instverify/dextu-size.mir
M llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dins-pos.mir
M llvm/test/CodeGen/Mips/instverify/dins-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
M llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
M llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
M llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/ext-pos.mir
M llvm/test/CodeGen/Mips/instverify/ext-size.mir
M llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
M llvm/test/CodeGen/Mips/instverify/ins-pos.mir
M llvm/test/CodeGen/Mips/instverify/ins-size.mir
M llvm/test/CodeGen/Mips/int-to-float-conversion.ll
M llvm/test/CodeGen/Mips/internalfunc.ll
M llvm/test/CodeGen/Mips/jumptable_labels.ll
M llvm/test/CodeGen/Mips/largeimm1.ll
M llvm/test/CodeGen/Mips/largeimmprinting.ll
M llvm/test/CodeGen/Mips/lazy-binding.ll
M llvm/test/CodeGen/Mips/lb1.ll
M llvm/test/CodeGen/Mips/lbu1.ll
M llvm/test/CodeGen/Mips/lh1.ll
M llvm/test/CodeGen/Mips/lhu1.ll
M llvm/test/CodeGen/Mips/llcarry.ll
M llvm/test/CodeGen/Mips/llvm-ir/abs.ll
M llvm/test/CodeGen/Mips/llvm-ir/add.ll
M llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
M llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
M llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll
M llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
M llvm/test/CodeGen/Mips/llvm-ir/call.ll
M llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
M llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll
M llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
M llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
M llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll
M llvm/test/CodeGen/Mips/llvm-ir/mul.ll
M llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll
M llvm/test/CodeGen/Mips/llvm-ir/not.ll
M llvm/test/CodeGen/Mips/llvm-ir/ret.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
M llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll
M llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll
M llvm/test/CodeGen/Mips/llvm-ir/sub.ll
M llvm/test/CodeGen/Mips/load-store-left-right.ll
M llvm/test/CodeGen/Mips/long-call-attr.ll
M llvm/test/CodeGen/Mips/long-call-mcount.ll
M llvm/test/CodeGen/Mips/long-calls.ll
M llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
M llvm/test/CodeGen/Mips/machineverifier.ll
M llvm/test/CodeGen/Mips/madd-msub.ll
M llvm/test/CodeGen/Mips/mcount.ll
M llvm/test/CodeGen/Mips/memcpy.ll
M llvm/test/CodeGen/Mips/micromips-addiu.ll
M llvm/test/CodeGen/Mips/micromips-addu16.ll
M llvm/test/CodeGen/Mips/micromips-and16.ll
M llvm/test/CodeGen/Mips/micromips-andi.ll
M llvm/test/CodeGen/Mips/micromips-attr.ll
M llvm/test/CodeGen/Mips/micromips-compact-branches.ll
M llvm/test/CodeGen/Mips/micromips-compact-jump.ll
M llvm/test/CodeGen/Mips/micromips-gp-rc.ll
M llvm/test/CodeGen/Mips/micromips-li.ll
M llvm/test/CodeGen/Mips/micromips-load-effective-address.ll
M llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
M llvm/test/CodeGen/Mips/micromips-not16.ll
M llvm/test/CodeGen/Mips/micromips-or16.ll
M llvm/test/CodeGen/Mips/micromips-shift.ll
M llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll
M llvm/test/CodeGen/Mips/micromips-subu16.ll
M llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll
M llvm/test/CodeGen/Mips/micromips-xor16.ll
M llvm/test/CodeGen/Mips/mips16_32_1.ll
M llvm/test/CodeGen/Mips/mips16fpe.ll
M llvm/test/CodeGen/Mips/mips3-spill-slot.ll
M llvm/test/CodeGen/Mips/mips32r6/compatibility.ll
M llvm/test/CodeGen/Mips/mips64-f128-call.ll
M llvm/test/CodeGen/Mips/mips64-libcall.ll
M llvm/test/CodeGen/Mips/mips64-sret.ll
M llvm/test/CodeGen/Mips/mips64directive.ll
M llvm/test/CodeGen/Mips/mips64ext.ll
M llvm/test/CodeGen/Mips/mips64extins.ll
M llvm/test/CodeGen/Mips/mips64fpimm0.ll
M llvm/test/CodeGen/Mips/mips64fpldst.ll
M llvm/test/CodeGen/Mips/mips64imm.ll
M llvm/test/CodeGen/Mips/mips64instrs.ll
M llvm/test/CodeGen/Mips/mips64intldst.ll
M llvm/test/CodeGen/Mips/mips64lea.ll
M llvm/test/CodeGen/Mips/mips64muldiv.ll
M llvm/test/CodeGen/Mips/mips64r6/compatibility.ll
M llvm/test/CodeGen/Mips/mips64shift.ll
M llvm/test/CodeGen/Mips/mips64signextendsesf.ll
M llvm/test/CodeGen/Mips/mips64sinttofpsf.ll
M llvm/test/CodeGen/Mips/mipslopat.ll
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
M llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
M llvm/test/CodeGen/Mips/misha.ll
M llvm/test/CodeGen/Mips/msa/2r.ll
M llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
M llvm/test/CodeGen/Mips/msa/2rf.ll
M llvm/test/CodeGen/Mips/msa/2rf_exup.ll
M llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/2rf_fq.ll
M llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/2rf_tq.ll
M llvm/test/CodeGen/Mips/msa/3r-a.ll
M llvm/test/CodeGen/Mips/msa/3r-b.ll
M llvm/test/CodeGen/Mips/msa/3r-c.ll
M llvm/test/CodeGen/Mips/msa/3r-d.ll
M llvm/test/CodeGen/Mips/msa/3r-i.ll
M llvm/test/CodeGen/Mips/msa/3r-m.ll
M llvm/test/CodeGen/Mips/msa/3r-p.ll
M llvm/test/CodeGen/Mips/msa/3r-s.ll
M llvm/test/CodeGen/Mips/msa/3r-v.ll
M llvm/test/CodeGen/Mips/msa/3r_4r.ll
M llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
M llvm/test/CodeGen/Mips/msa/3r_splat.ll
M llvm/test/CodeGen/Mips/msa/3rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
M llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
M llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/3rf_q.ll
M llvm/test/CodeGen/Mips/msa/arithmetic.ll
M llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
M llvm/test/CodeGen/Mips/msa/basic_operations.ll
M llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
M llvm/test/CodeGen/Mips/msa/bit.ll
M llvm/test/CodeGen/Mips/msa/bitcast.ll
M llvm/test/CodeGen/Mips/msa/bitwise.ll
M llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
M llvm/test/CodeGen/Mips/msa/compare.ll
M llvm/test/CodeGen/Mips/msa/compare_float.ll
M llvm/test/CodeGen/Mips/msa/elm_copy.ll
M llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
M llvm/test/CodeGen/Mips/msa/elm_insv.ll
M llvm/test/CodeGen/Mips/msa/elm_move.ll
M llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
M llvm/test/CodeGen/Mips/msa/emergency-spill.mir
M llvm/test/CodeGen/Mips/msa/endian.ll
M llvm/test/CodeGen/Mips/msa/fexuprl.ll
M llvm/test/CodeGen/Mips/msa/frameindex.ll
M llvm/test/CodeGen/Mips/msa/i10.ll
M llvm/test/CodeGen/Mips/msa/i5-a.ll
M llvm/test/CodeGen/Mips/msa/i5-b.ll
M llvm/test/CodeGen/Mips/msa/i5-c.ll
M llvm/test/CodeGen/Mips/msa/i5-m.ll
M llvm/test/CodeGen/Mips/msa/i5-s.ll
M llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
M llvm/test/CodeGen/Mips/msa/i8.ll
M llvm/test/CodeGen/Mips/msa/immediates-bad.ll
M llvm/test/CodeGen/Mips/msa/immediates.ll
M llvm/test/CodeGen/Mips/msa/inline-asm.ll
M llvm/test/CodeGen/Mips/msa/ldr_str.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
M llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
M llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll
M llvm/test/CodeGen/Mips/msa/nori.b.ll
M llvm/test/CodeGen/Mips/msa/remat-ldi.ll
M llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
M llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
M llvm/test/CodeGen/Mips/msa/shift_no_and.ll
M llvm/test/CodeGen/Mips/msa/shuffle.ll
M llvm/test/CodeGen/Mips/msa/special.ll
M llvm/test/CodeGen/Mips/msa/spill.ll
M llvm/test/CodeGen/Mips/msa/vec.ll
M llvm/test/CodeGen/Mips/msa/vecs10.ll
M llvm/test/CodeGen/Mips/mul.ll
M llvm/test/CodeGen/Mips/mulll.ll
M llvm/test/CodeGen/Mips/mulull.ll
M llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
M llvm/test/CodeGen/Mips/neg1.ll
M llvm/test/CodeGen/Mips/nmadd.ll
M llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll
M llvm/test/CodeGen/Mips/not1.ll
M llvm/test/CodeGen/Mips/null.ll
M llvm/test/CodeGen/Mips/o32_cc.ll
M llvm/test/CodeGen/Mips/o32_cc_vararg.ll
M llvm/test/CodeGen/Mips/octeon.ll
M llvm/test/CodeGen/Mips/octeon_popcnt.ll
M llvm/test/CodeGen/Mips/optimize-fp-math.ll
M llvm/test/CodeGen/Mips/or1.ll
M llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
M llvm/test/CodeGen/Mips/pr33682.ll
M llvm/test/CodeGen/Mips/pr33978.ll
M llvm/test/CodeGen/Mips/prevent-hoisting.ll
M llvm/test/CodeGen/Mips/private.ll
M llvm/test/CodeGen/Mips/ra-allocatable.ll
M llvm/test/CodeGen/Mips/rem.ll
M llvm/test/CodeGen/Mips/remat-immed-load.ll
M llvm/test/CodeGen/Mips/remu.ll
M llvm/test/CodeGen/Mips/return-vector.ll
M llvm/test/CodeGen/Mips/return_address.ll
M llvm/test/CodeGen/Mips/return_address_err.ll
M llvm/test/CodeGen/Mips/rotate.ll
M llvm/test/CodeGen/Mips/sb1.ll
M llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezSlti.ll
M llvm/test/CodeGen/Mips/selectcc.ll
M llvm/test/CodeGen/Mips/selectiondag-optlevel.ll
M llvm/test/CodeGen/Mips/seleq.ll
M llvm/test/CodeGen/Mips/seleqk.ll
M llvm/test/CodeGen/Mips/selgek.ll
M llvm/test/CodeGen/Mips/selgt.ll
M llvm/test/CodeGen/Mips/selle.ll
M llvm/test/CodeGen/Mips/selltk.ll
M llvm/test/CodeGen/Mips/selne.ll
M llvm/test/CodeGen/Mips/selnek.ll
M llvm/test/CodeGen/Mips/selpat.ll
M llvm/test/CodeGen/Mips/setcc-se.ll
M llvm/test/CodeGen/Mips/seteq.ll
M llvm/test/CodeGen/Mips/seteqz.ll
M llvm/test/CodeGen/Mips/setge.ll
M llvm/test/CodeGen/Mips/setgek.ll
M llvm/test/CodeGen/Mips/setle.ll
M llvm/test/CodeGen/Mips/setlt.ll
M llvm/test/CodeGen/Mips/setltk.ll
M llvm/test/CodeGen/Mips/setne.ll
M llvm/test/CodeGen/Mips/setuge.ll
M llvm/test/CodeGen/Mips/setugt.ll
M llvm/test/CodeGen/Mips/setule.ll
M llvm/test/CodeGen/Mips/setult.ll
M llvm/test/CodeGen/Mips/setultk.ll
M llvm/test/CodeGen/Mips/sh1.ll
M llvm/test/CodeGen/Mips/shift-parts.ll
M llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
M llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll
M llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
M llvm/test/CodeGen/Mips/sll1.ll
M llvm/test/CodeGen/Mips/sll2.ll
M llvm/test/CodeGen/Mips/slt.ll
M llvm/test/CodeGen/Mips/spill-copy-acreg.ll
M llvm/test/CodeGen/Mips/sra1.ll
M llvm/test/CodeGen/Mips/sra2.ll
M llvm/test/CodeGen/Mips/srl1.ll
M llvm/test/CodeGen/Mips/srl2.ll
M llvm/test/CodeGen/Mips/stack-alignment.ll
M llvm/test/CodeGen/Mips/stackcoloring.ll
M llvm/test/CodeGen/Mips/stchar.ll
M llvm/test/CodeGen/Mips/stldst.ll
M llvm/test/CodeGen/Mips/sub1.ll
M llvm/test/CodeGen/Mips/sub2.ll
M llvm/test/CodeGen/Mips/swzero.ll
M llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll
M llvm/test/CodeGen/Mips/thread-pointer.ll
M llvm/test/CodeGen/Mips/tls-alias.ll
M llvm/test/CodeGen/Mips/tnaked.ll
M llvm/test/CodeGen/Mips/trap.ll
M llvm/test/CodeGen/Mips/uitofp.ll
M llvm/test/CodeGen/Mips/ul1.ll
M llvm/test/CodeGen/Mips/unaligned-memops.ll
M llvm/test/CodeGen/Mips/unalignedload.ll
M llvm/test/CodeGen/Mips/vector-load-store.ll
M llvm/test/CodeGen/Mips/vector-setcc.ll
M llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
M llvm/test/CodeGen/Mips/vr4300-mulmul.ll
M llvm/test/CodeGen/Mips/weak.ll
M llvm/test/CodeGen/Mips/whitespace.ll
M llvm/test/CodeGen/Mips/xor1.ll
M llvm/test/CodeGen/Mips/zeroreg.ll
A llvm/test/CodeGen/PowerPC/ppc64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
A llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
A llvm/test/CodeGen/RISCV/xray-attribute-instrumentation.ll
A llvm/test/CodeGen/SystemZ/stackmap-args.ll
M llvm/test/CodeGen/X86/bfloat.ll
A llvm/test/CodeGen/X86/stackmap-args.ll
M llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
M llvm/test/DebugInfo/Mips/tls.ll
R llvm/test/MC/ELF/debug-hash-file-empty-dwarf.s
A llvm/test/Transforms/Inline/promote-call-bitwidth.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/predicated-reduction.ll
A llvm/test/Transforms/SLPVectorizer/fix-113880.ll
M llvm/test/tools/llvm-profdata/memprof-yaml.test
M llvm/test/tools/llvm-readobj/ELF/note-core.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
M llvm/utils/gn/secondary/clang/lib/Serialization/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
M mlir/lib/Conversion/GPUToNVVM/CMakeLists.txt
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
A mlir/test/Dialect/Linalg/td/vectorize-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M polly/lib/CodeGen/CodeGeneration.cpp
M polly/test/CodeGen/LoopParallelMD/single_loop_param_parallel.ll
M polly/test/CodeGen/MemAccess/codegen_address_space.ll
M polly/test/CodeGen/MemAccess/create_arrays.ll
M polly/test/CodeGen/MemAccess/different_types.ll
M polly/test/CodeGen/MemAccess/generate-all.ll
M polly/test/CodeGen/OpenMP/alias-metadata.ll
M polly/test/CodeGen/OpenMP/new_multidim_access.ll
M polly/test/CodeGen/RuntimeDebugBuilder/combine_different_values.ll
M polly/test/CodeGen/annotated_alias_scopes.ll
M polly/test/CodeGen/non-affine-phi-node-expansion-2.ll
M polly/test/CodeGen/non_affine_float_compare.ll
M polly/test/CodeGen/partial_write_array.ll
M polly/test/CodeGen/partial_write_impossible_restriction.ll
M polly/test/CodeGen/phi_loop_carried_float.ll
M polly/test/CodeGen/phi_loop_carried_float_escape.ll
M polly/test/CodeGen/scev-backedgetaken.ll
M polly/test/CodeGen/stmt_split_no_dependence.ll
M polly/test/ScopInfo/int2ptr_ptr2int.ll
M polly/test/ScopInfo/int2ptr_ptr2int_2.ll
M utils/bazel/.bazelrc
M utils/bazel/llvm-project-overlay/libc/test/src/strings/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/lit_test.bzl
Log Message:
-----------
Merge branch 'main' into users/meinersbur/flang_runtime_move-files
Commit: 6c7e5827eda26990e872eb7c3f0d7866ee3c3171
https://github.com/llvm/llvm-project/commit/6c7e5827eda26990e872eb7c3f0d7866ee3c3171
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
[SelectionDAG] Don't call ComputeValueVTs for "demote register" (NFC) (#119268)
`ComputeValueVTs` only breaks down aggregate types. For pointer types it
is equivalent to calling `TargetLoweringBase::getPointerTy`.
Commit: 8eb12f6775d288eece9a2bf090d2675c025bf457
https://github.com/llvm/llvm-project/commit/8eb12f6775d288eece9a2bf090d2675c025bf457
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/AMDGPU/sopk.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] Support s_endpgm_ordered_ps_done on GFX11 (#119230)
Support assembly/disassembly of this instruction for compatibility with
SP3, even though it has no use in GFX11. It is fully removed in GFX12.
Commit: 3057ac1c9a76b9957a6bcdd0595788ac342dba6b
https://github.com/llvm/llvm-project/commit/3057ac1c9a76b9957a6bcdd0595788ac342dba6b
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
[SelectionDAG] Fix "unused variable" warnings after #119268 (NFC) (#119550)
Commit: c69f8296f313d4b0766b322fea121c576bd4ec01
https://github.com/llvm/llvm-project/commit/c69f8296f313d4b0766b322fea121c576bd4ec01
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
Log Message:
-----------
[X86][StrictFP] Add widening support for STRICT_FMIN/STRICT_FMAX (#119391)
Fixes: #119422
Commit: 0100c631f85480ecdf1b35f2aedbfc0200a81174
https://github.com/llvm/llvm-project/commit/0100c631f85480ecdf1b35f2aedbfc0200a81174
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/docs/Reference.rst
A llvm/docs/UndefinedBehavior.rst
Log Message:
-----------
[docs] Add guide about Undefined Behavior (#119220)
Thanks Antonio Frighetto, John Regehr, and Nikita Popov for reviewing this!
Commit: 04379c98638ac3901257b5fa319f9ece828af767
https://github.com/llvm/llvm-project/commit/04379c98638ac3901257b5fa319f9ece828af767
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/Basic/FileEntry.h
M clang/lib/Basic/SourceManager.cpp
M llvm/include/llvm/Support/AutoConvert.h
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/MemoryBuffer.cpp
Log Message:
-----------
[SystemZ][z/OS] Update autoconversion functions to improve support for UTF-8 (#98652)
This fixes the following error when reading source and header files on
z/OS: error: source file is not valid UTF-8
Commit: 5e007afa9d4f175decc328ee89533a5fe89be99b
https://github.com/llvm/llvm-project/commit/5e007afa9d4f175decc328ee89533a5fe89be99b
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
Log Message:
-----------
[AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (#118589)
Presently, compiler selectivelly adds nop when opsel != 0 i.e. only when
partially writing to high bytes.
Experiments in SWDEV-499733 and SWDEV-501347 suggest that we need nop
for above cases irrespective of opsel values.
Note: We might need to add few others into the same table.
Commit: b1d8c60dd479d9c5d58bcfe33db57b68f834938d
https://github.com/llvm/llvm-project/commit/b1d8c60dd479d9c5d58bcfe33db57b68f834938d
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
Log Message:
-----------
[AArch64] Implement FP8 SVE Intrinsics for narrowing conversions (#118124)
This patch adds the following instrinsics:
* Half-precision and BFloat16 convert, narrow, and interleave to 8-bit
floating-point.
// Variant is also available for: _bf16_x2
svmfloat8_t svcvtn_mf8[_f16_x2]_fpm(svfloat16x2_t zn, fpm_t fpm);
* Single-precision convert, narrow, and interleave to 8-bit
floating-point (top and bottom).
svmfloat8_t svcvtnt_mf8[_f32_x2]_fpm(svmfloat8_t zd, svfloat32x2_t zn,
fpm_t fpm);
svmfloat8_t svcvtnb_mf8[_f32_x2]_fpm(svfloat32x2_t zn, fpm_t fpm);
Commit: 854ea0cf18e71608b2354a50872251c99628a6c2
https://github.com/llvm/llvm-project/commit/854ea0cf18e71608b2354a50872251c99628a6c2
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
Log Message:
-----------
[win/asan] GetInstructionSize: Make `83 EC XX` a generic entry. (#119537)
This consolidates the two different lines for x86 and x86_64 into a
single line for both architectures.
And adds a test line.
CC: @zmodem
Commit: 03019c687f00cdd9d05fc1ace329a438c3ff6364
https://github.com/llvm/llvm-project/commit/03019c687f00cdd9d05fc1ace329a438c3ff6364
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/test/Driver/fveclib.c
M flang/test/Driver/fveclib.f90
Log Message:
-----------
[clang][driver] When -fveclib=ArmPL flag is in use, always link against libamath (#116432)
Using `-fveclib=ArmPL` without `-lamath` likely effects in the link-time
errors.
Commit: bc1f3eb59333d32797db234c0edf4dc270469b0e
https://github.com/llvm/llvm-project/commit/bc1f3eb59333d32797db234c0edf4dc270469b0e
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
Log Message:
-----------
[DAGCombiner] Pre-commit test case for ReduceLoadOpStoreWidth. NFC
Adding test cases related to narrowing of load-op-store sequences.
ReduceLoadOpStoreWidth isn't careful enough, so it may end up
creating load/store operations that access memory outside the region
touched by the original load/store. Using ARM as a target for the
test cases to show what happens for both little-endian and big-endian.
This patch also adds a way to override the TLI.isNarrowingProfitable
check in DAGCombiner::ReduceLoadOpStoreWidth by using the option
-combiner-reduce-load-op-store-width-force-narrowing-profitable.
Idea is that it should be simpler to for example add lit tests
verifying that the code is correct for big-endian (which otherwise
is difficult since there are no in-tree big-endian targets that
is overriding TLI.isNarrowingProfitable).
This is a pre-commit for
https://github.com/llvm/llvm-project/pull/119203
Commit: 22780f808a6dba83bad9390f762095f263324df9
https://github.com/llvm/llvm-project/commit/22780f808a6dba83bad9390f762095f263324df9
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
M llvm/test/CodeGen/X86/store_op_load_fold.ll
Log Message:
-----------
[DAGCombiner] Fix to avoid writing outside original store in ReduceLoadOpStoreWidth (#119203)
DAGCombiner::ReduceLoadOpStoreWidth could replace memory accesses
with more narrow loads/store, although sometimes the new load/store
would touch memory outside the original object. That seemed wrong
and this patch is simply avoiding doing the DAG combine in such
situations.
Also simplifying the expression used to align ShAmt down to a multiple
of NewBW. Subtracting (ShAmt % NewBW) should do the same thing as the
old more complicated expression.
Intention is to follow up with a patch that make more attempts, trying
to align the memory accesses at other offsets, allowing to trigger
the transform in more situations. The current strategy for deciding
size (NewBW) and offset (ShAmt) for the narrowed operations are a bit
ad-hoc, and not really considering big endian memory order in same
way as little endian.
Commit: b4b819ce98f1d77d29ec492f0230018fd633a117
https://github.com/llvm/llvm-project/commit/b4b819ce98f1d77d29ec492f0230018fd633a117
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/tma_store_reduce.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Add Op for TMA Store with reduction (#118853)
PR #116854 adds intrinsics for TMA Store with reduction.
This patch adds an NVVM Dialect Op for the same.
* Lit tests are added to verify the lowering to LLVM intrinsics and
invalid cases.
* The common verifier method is updated to handle im2col modes without
offsets.
This helps Ops like TMA Store, TMA StoreReduce etc.
* The nvvmir.mlir test file is already large. So, this patch adds the
tests for this Op
in a new file under a separate "nvvm/" directory.
[mlir/test/Target/LLVMIR/"nvvm"/tma_store_reduce.mlir]
PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: d416cae180a5c7e7325c0b55818056e328633a61
https://github.com/llvm/llvm-project/commit/d416cae180a5c7e7325c0b55818056e328633a61
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode][NFC] Use Pointer::pointToSameBlock (#119552)
block() requires the pointer to be a block pointer.
Commit: e0c6088bcb5746795f04ab0bf53cec1cfea2480e
https://github.com/llvm/llvm-project/commit/e0c6088bcb5746795f04ab0bf53cec1cfea2480e
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][nfc] Update vectorize-tensor-extract.mlir (3/N) (#119121)
Tests in "vectorize-tensor-extract.mlir" are inconsistent and would
benefit from refactoring to:
* Clearly categorize tests into "contiguous load," "gather load," and
"scalar load + broadcast" cases, reflecting the structure of
tensor.extract vectorization.
* Unify variable naming (both MLIR and FileCheck).
* Ensure all tests exercise unmasked vectorization (masked vectorization
is covered in "vectorize-tensor-extract-masked.mlir").
* Improve and standardize formatting.
These changes will make it easier to identify the test cases being
exercised and simplify future maintenance or refactoring.
This is patch 3/N in the series. Below is a summary of the changes in
this patch.
----------------------------------------------------------------------
Summary of patch 3/N
----------------------------------------------------------------------
* Cluster all tests for "scalar load + broadcast" together
* Unify MLIR and FileCheck variable names, e.g. `%input`, `%output` ->
`%src`, `%init`.
Note, I haven't changed test function names to make it easier to track
changes (this PR is mostly about moving code). I will send a seperate PR
to rename the tests.
----------------------------------------------------------------------
Previous patches
----------------------------------------------------------------------
* https://github.com/llvm/llvm-project/pull/118977
* https://github.com/llvm/llvm-project/pull/119080
Commit: ad0fbb033d26edafab51e67232c189a52afc4c52
https://github.com/llvm/llvm-project/commit/ad0fbb033d26edafab51e67232c189a52afc4c52
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add vl-opt-op-info tests for unit strided and strided stores (#119465)
I don't include getOperandInfo for the loads, since they don't take a
vector use operand, and we don't include the loads in isSupportedInstr
so we will never call getOperandInfo on the vector destination of these
instructions.
Don't add support for VSM since we don't have any mask producing
instructions in isSupportedInstr at the moment.
Commit: 323bedd0d60a9f4c04015687326eba1e96f34b04
https://github.com/llvm/llvm-project/commit/323bedd0d60a9f4c04015687326eba1e96f34b04
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxx/include/experimental/iterator
M libcxx/include/experimental/memory
M libcxx/include/experimental/propagate_const
M libcxx/include/experimental/simd
M libcxx/include/experimental/type_traits
M libcxx/include/experimental/utility
M libcxx/include/ext/hash_map
M libcxx/include/ext/hash_set
Log Message:
-----------
[libc++][C++03] Add #if 0 to the experimental/ and ext/ headers as well (#119541)
This has already been done for the most headers in
https://github.com/llvm/llvm-project/pull/119234, but I
forgot to also do it for the experimental/ and ext/ headers.
This is part of https://discourse.llvm.org/t/rfc-freezing-c-03-headers-in-libc.
Commit: 40986feda8b1437ed475b144d5b9a208b008782a
https://github.com/llvm/llvm-project/commit/40986feda8b1437ed475b144d5b9a208b008782a
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/LLVMContext.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
Log Message:
-----------
Revert "DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm" (#119575)
Reverts llvm/llvm-project#119485
Breaks builders, details in llvm/llvm-project#119485
Commit: cb4f4a8a4dd18bf00604b49faadd7b0ee4394d3d
https://github.com/llvm/llvm-project/commit/cb4f4a8a4dd18bf00604b49faadd7b0ee4394d3d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/sme-abi-assert.c
R compiler-rt/lib/builtins/aarch64/sme-abi-init.c
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/fmv/baremetal.inc
Log Message:
-----------
[compiler-rt][AArch64] Rewrite SME routines to all use __aarch64_cpu_features. (#119414)
When #92921 added the `__arm_get_current_vg` functionality, it used the
FMV feature bits mechanism rather than the mechanism that was previously
added for SME which called `getauxval` on Linux platforms or
`__aarch64_sme_accessible` required for baremetal libraries. It is
better to always use `__aarch64_cpu_features`.
For baremetal we still need to rely on `__arm_sme_accessible` to
initialise the struct.
Commit: 10ad2135ab33302a55fc2e8a42e6001a44aae0bc
https://github.com/llvm/llvm-project/commit/10ad2135ab33302a55fc2e8a42e6001a44aae0bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Move Chad Rosier to inactive maintainers
Chad has not been involved with LLVM for more than five years, so
move him to the inactive maintainers.
Unfortunately, there doesn't seem to be a clear person to take up
FastISel maintainership.
Commit: 3787fbf0402b4e03e316c13231f8873769701250
https://github.com/llvm/llvm-project/commit/3787fbf0402b4e03e316c13231f8873769701250
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
Log Message:
-----------
[RISCV] Enable merging of external globals by default (#117880)
This follows up #115495 by enabling merging of external globals by
default, which had been left as a next step in order to make the
previous change more incremental and so we can more easily narrow down
on any identified regressions.
Enabling merging of external globals matches what Arm does (for non
mach-o targets), though AArch64 doesn't as there were [some
concerns](https://reviews.llvm.org/D61947) it might cause regressions in
some cases.
See https://github.com/llvm/llvm-project/pull/117880 for benchmark figures and discussion.
Commit: 673c324ae3653cf62d67c5acbee1126e9eb6843e
https://github.com/llvm/llvm-project/commit/673c324ae3653cf62d67c5acbee1126e9eb6843e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
Log Message:
-----------
[VectorCombine] foldInsExtVectorToShuffle - canonicalize new shuffle(undef,x) -> shuffle(x,undef).
foldInsExtVectorToShuffle is likely to be inserting into an undef value, so make sure we've canonicalized this to the RHS in the folded shuffle to help further VectorCombine folds.
Minor tweak to help #34072
Commit: 00e1cc4c9d002c78cf890b630343b052ebca0399
https://github.com/llvm/llvm-project/commit/00e1cc4c9d002c78cf890b630343b052ebca0399
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Lower/OpenMP/Todo/atomic-compare-fail.f90
M flang/test/Parser/OpenMP/atomic-unparse.f90
M flang/test/Semantics/OpenMP/atomic-compare.f90
M flang/test/Semantics/OpenMP/atomic01.f90
M flang/test/Semantics/OpenMP/atomic05.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP]Add support for fail clause (#118683)
Support the atomic compare option of a fail(memory-order) clauses.
Additional tests introduced to check that parsing and semantics checks
for the new clause is handled.
Lowering for atomic compare is still unsupported and wil end in a TOOD
(aka "Not yet implemented"). A test for this case with the fail clause
is also present.
Commit: 624cc7048f604ed1087f63fdbe4cbf40f1d35b69
https://github.com/llvm/llvm-project/commit/624cc7048f604ed1087f63fdbe4cbf40f1d35b69
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/AST/ExprObjC.h
M clang/include/clang/AST/Redeclarable.h
M clang/include/clang/AST/TemplateBase.h
Log Message:
-----------
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#119523)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 8b63bfbf6dd2ad0efd221407755300942a7ca35f
https://github.com/llvm/llvm-project/commit/8b63bfbf6dd2ad0efd221407755300942a7ca35f
Author: qt-tatiana <tatiana.borisova at qt.io>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/CMakeLists.txt
M clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/modernize/use-integer-sign-comparison.rst
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-integer-sign-comparison.cpp
Log Message:
-----------
[clang-tidy] Create a check for signed and unsigned integers comparison (#113144)
- modernize-use-integer-sign-comparison replaces comparisons between
signed and unsigned integers with their safe C++20 ``std::cmp_*``
alternative, if available.
Commit: 08f904011f4b17e46b7616737a5dec01e3563c80
https://github.com/llvm/llvm-project/commit/08f904011f4b17e46b7616737a5dec01e3563c80
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
Log Message:
-----------
[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns (#119559)
Mask/Bool vectors are often bitcast to/from scalar integers, in particular when concatenating mask results, often this is due to the difficulties of working with vector of bools on C/C++. On x86 this typically involves the MOVMSK/KMOV instructions.
To concatenate bool masks, these are typically cast to scalars, which are then zero-extended, shifted and OR'd together.
This patch attempts to match these scalar concatenation patterns and convert them to vector shuffles instead. This in turn often assists with further vector combines, depending on the cost model.
Fixes #111431
Commit: 03661fbe45e70bde2984a5fc0feab6396407a33b
https://github.com/llvm/llvm-project/commit/03661fbe45e70bde2984a5fc0feab6396407a33b
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/docs/UndefinedBehavior.rst
Log Message:
-----------
[docs][UB] add section on poison propagation through select
Examples from Nikita Popov, thank you!
Commit: 53544fc15f08687c14becced4ecc22c2356265cd
https://github.com/llvm/llvm-project/commit/53544fc15f08687c14becced4ecc22c2356265cd
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/test/ELF/lto/internalize-exportdyn.ll
Log Message:
-----------
[ELF] Respect ltoCanOmit for symbols in non-prevailing COMDAT
A linkonce_odr definition can be omitted in LTO compilation if
`canBeOmittedFromSymbolTable()` is true in all bitcode files.
Currently, we don't respect the `canBeOmittedFromSymbolTable()` bit from
symbols in a non-prevailing COMDAT, which could lead to incorrect
omission of a definition when merging a prevailing linkonce_odr and a
non-prevailing weak_odr, e.g. an implicit template instantiation and an
explicit template instantiation.
To fix #111341, allow the non-prevailing COMDAT code path to clear the
`ltoCanOmit` bit, so that `VisibleToRegularObj` could be false in
LTO.cpp. We could resolve either an Undefined or a Defined. For
simplicity, just use a Defined like the prevailing case (similar to how
we resolve symbols in ObjectFile COMDAT reviews.llvm.org/D120626).
Pull Request: https://github.com/llvm/llvm-project/pull/119332
Commit: 0663a73104424a1e9e7416bddb4fe3bec7129a2b
https://github.com/llvm/llvm-project/commit/0663a73104424a1e9e7416bddb4fe3bec7129a2b
Author: Haopeng Liu <153236845+haopliu at users.noreply.github.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
Revert "[DSE] Enable initializes improvement" (#119590)
Reverts llvm/llvm-project#119116
Commit: 1946d32f1fdfb2c4d5e866a5c1c5c32b8cdad5b8
https://github.com/llvm/llvm-project/commit/1946d32f1fdfb2c4d5e866a5c1c5c32b8cdad5b8
Author: Csanád Hajdú <csanad.hajdu at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[Clang] Improve error for `-fsanitize=function/kcfi -mexecute-only` incompatibility (#118816)
The current error message when using the `-fsanitize=function
-mexecute-only` flags together points to the target triple as the reason
that `-fsanitize=function` is not allowed to be used, even when the
function sanitizer is otherwise supported on the target when not using
`-mexecute-only`.
The error message is improved to give `-mexecute-only` as the reason for
disallowing `-fsanitize=function` if it was passed to the driver.
Fixes https://github.com/llvm/llvm-project/issues/117974
Commit: 92bf1aa399a00c6902e80090074fff66fc5416a9
https://github.com/llvm/llvm-project/commit/92bf1aa399a00c6902e80090074fff66fc5416a9
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/modernize/BUILD.gn
Log Message:
-----------
[gn build] Port 8b63bfbf6dd2
Commit: 9b94869942bb71daeb119e7701d806ae0003cc0d
https://github.com/llvm/llvm-project/commit/9b94869942bb71daeb119e7701d806ae0003cc0d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use front instead of begin in a unit test (NFC) (#119501)
"front" allows us to drop a dereference.
Commit: 9aa5848d5cb03cd024b1ebb2f8a5225917f63881
https://github.com/llvm/llvm-project/commit/9aa5848d5cb03cd024b1ebb2f8a5225917f63881
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Drop curly braces on small for loops (NFC) (#119516)
Commit: 66edefaee5e87baabe2367cf1dd82ef40cee8c86
https://github.com/llvm/llvm-project/commit/66edefaee5e87baabe2367cf1dd82ef40cee8c86
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/ProfileData/MemProf.h
A llvm/include/llvm/ProfileData/MemProfYAML.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Move YAML support to MemProfYAML.h (NFC) (#119515)
The YAML support is increasing in size, so this patch moves it to a
separate file.
Commit: 7b2d592a1971fccb8d3cf386d1bc9185b3b1198f
https://github.com/llvm/llvm-project/commit/7b2d592a1971fccb8d3cf386d1bc9185b3b1198f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxx/test/libcxx/feature_test_macro/version_header.sh.py
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Fix test FTM header guard
That template is actually not used to generate the version header yet,
but we can at least fix the include guards which are clearly incorrect.
Commit: b0b546d44777eb1fa25995384876bd14a006a929
https://github.com/llvm/llvm-project/commit/b0b546d44777eb1fa25995384876bd14a006a929
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
M libunwind/CMakeLists.txt
Log Message:
-----------
[libc++abi] Provide an explicit error when trying to build for MSVC (#119370)
Fixes #119322
Commit: 3c464d23682b0f9e6f70965e8f8f3861c9ba5417
https://github.com/llvm/llvm-project/commit/3c464d23682b0f9e6f70965e8f8f3861c9ba5417
Author: Eliud de León <eliud.deleon.10 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
A mlir/include/mlir-c/Dialect/EmitC.h
M mlir/lib/CAPI/Dialect/CMakeLists.txt
A mlir/lib/CAPI/Dialect/EmitC.cpp
M mlir/python/CMakeLists.txt
A mlir/python/mlir/dialects/EmitC.td
A mlir/python/mlir/dialects/emitc.py
A mlir/test/python/dialects/emitc_dialect.py
Log Message:
-----------
[mlir][emitc] Add support for C-API/python binding to EmitC dialect (#119476)
Added EmitC dialect bindings.
Commit: d65a4bcf0d76932e2f6078a7fc7db6ab922fd3fb
https://github.com/llvm/llvm-project/commit/d65a4bcf0d76932e2f6078a7fc7db6ab922fd3fb
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/CMakeLists.txt
M clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/modernize/use-integer-sign-comparison.rst
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-integer-sign-comparison.cpp
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/AST/ExprObjC.h
M clang/include/clang/AST/Redeclarable.h
M clang/include/clang/AST/TemplateBase.h
M clang/include/clang/Basic/FileEntry.h
M clang/include/clang/Basic/arm_sve.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
M clang/test/Driver/fsanitize.c
M clang/test/Driver/fveclib.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/sme-abi-assert.c
R compiler-rt/lib/builtins/aarch64/sme-abi-init.c
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/fmv/baremetal.inc
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/test/Driver/fveclib.f90
A flang/test/Lower/OpenMP/Todo/atomic-compare-fail.f90
M flang/test/Parser/OpenMP/atomic-unparse.f90
M flang/test/Semantics/OpenMP/atomic-compare.f90
M flang/test/Semantics/OpenMP/atomic01.f90
M flang/test/Semantics/OpenMP/atomic05.f90
M libcxx/include/experimental/iterator
M libcxx/include/experimental/memory
M libcxx/include/experimental/propagate_const
M libcxx/include/experimental/simd
M libcxx/include/experimental/type_traits
M libcxx/include/experimental/utility
M libcxx/include/ext/hash_map
M libcxx/include/ext/hash_set
M libcxx/test/libcxx/feature_test_macro/version_header.sh.py
M libcxx/utils/generate_feature_test_macro_components.py
M libcxxabi/CMakeLists.txt
M libunwind/CMakeLists.txt
M lld/ELF/InputFiles.cpp
M lld/test/ELF/lto/internalize-exportdyn.ll
M llvm/Maintainers.md
M llvm/docs/Reference.rst
A llvm/docs/UndefinedBehavior.rst
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/ProfileData/MemProf.h
A llvm/include/llvm/ProfileData/MemProfYAML.h
M llvm/include/llvm/Support/AutoConvert.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/MemoryBuffer.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
A llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
M llvm/test/CodeGen/X86/store_op_load_fold.ll
M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
M llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/AMDGPU/sopk.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
M llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/modernize/BUILD.gn
A mlir/include/mlir-c/Dialect/EmitC.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/CAPI/Dialect/CMakeLists.txt
A mlir/lib/CAPI/Dialect/EmitC.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/python/CMakeLists.txt
A mlir/python/mlir/dialects/EmitC.td
A mlir/python/mlir/dialects/emitc.py
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
A mlir/test/Target/LLVMIR/nvvm/tma_store_reduce.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
A mlir/test/python/dialects/emitc_dialect.py
Log Message:
-----------
Merge branch 'main' into users/meinersbur/flang_runtime_move-files
Compare: https://github.com/llvm/llvm-project/compare/e99f71af4f8a...d65a4bcf0d76
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