[all-commits] [llvm/llvm-project] 9bb29c: [RISCV][VLOPT] Add support for bitwise logical, si...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9bb29c3dc19aad6d89fc4bfc488479d8b74ee4ff
      https://github.com/llvm/llvm-project/commit/9bb29c3dc19aad6d89fc4bfc488479d8b74ee4ff
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-12-10 (Tue, 10 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

  Log Message:
  -----------
  [RISCV][VLOPT] Add support for bitwise logical, single width shift, and vector move (#119412)

Add support and tests for these instructions. Get operand info test
exist in llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir



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