[all-commits] [llvm/llvm-project] c1afca: [RISCV] Match deinterleave(4, 8) shuffles to SHL/TR...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c1afcaf33b03638fd533d14b0d3f65cd5c50755c
      https://github.com/llvm/llvm-project/commit/c1afcaf33b03638fd533d14b0d3f65cd5c50755c
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-12-03 (Tue, 03 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

  Log Message:
  -----------
  [RISCV] Match deinterleave(4,8) shuffles to SHL/TRUNC when legal (#118509)

We can extend the existing SHL+TRUNC lowering used for deinterleave2 for
deinterleave4, and deinterleave8 when the result types are small enough
to allow the shift to be legal. On RV64, this means i8 and i16 results
for deinterleave4 and i8 results for deinterleave8.



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