[all-commits] [llvm/llvm-project] c4645f: [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c4645ffedacad18e4cd1dd372288aa55178b1c44
      https://github.com/llvm/llvm-project/commit/c4645ffedacad18e4cd1dd372288aa55178b1c44
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2024-11-28 (Thu, 28 Nov 2024)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/MC/RISCV/xqcicsr-invalid.s
    A llvm/test/MC/RISCV/xqcicsr-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.



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