[all-commits] [llvm/llvm-project] c8ee1e: AMDGPU: Builtin & CodeGen support for v_cvt_scalef...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c8ee1ee0571c5e49bee42983a8b9d8db0243c001
      https://github.com/llvm/llvm-project/commit/c8ee1ee0571c5e49bee42983a8b9d8db0243c001
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-11-26 (Tue, 26 Nov 2024)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsAMDGPU.def
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
    M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll

  Log Message:
  -----------
  AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (#117794)

These instructions have non-standard use of OPSEL bits to select
dest write byte. The src2_modifiers operand is used without having
its corresponding src2 operand by introducing dummy src2.

OPSEL ASM OPSEL Syntax: opsel:[a,b,c,d]
a & b are meaningless, c & d together decides byte to write in dst reg.

Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>



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