[all-commits] [llvm/llvm-project] eff60d: [RISCV][GISel] Make extended loads and truncating ...

Tue Nov 19 13:26:53 PST 2024

  Branch: refs/heads/users/alexey-bataev/spr/slpmodel-reduction_addextn-x-i1-as-extctpopbitcast-n-x-i1-to-int-n
  Home:   https://github.com/llvm/llvm-project
  Commit: eff60d83b0533954eda153fbbabb3e99d46bde94
      https://github.com/llvm/llvm-project/commit/eff60d83b0533954eda153fbbabb3e99d46bde94
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

This addresses some failures I've seen in testing on real code.

  Commit: ca79e126482084fe4681dd777fdd2948d4e7c81b
      https://github.com/llvm/llvm-project/commit/ca79e126482084fe4681dd777fdd2948d4e7c81b
  Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
    M flang/test/Fir/CUDA/cuda-implicit-device-global.f90

  Log Message:
  -----------
  [flang][cuda] Handle implicit global in cuf kernel and nested statement (#116846)

Update the implicit global detection by looking for them in the CUF
kernel and also update to a walk so nested `fir.address_of` in nested
statement are also accounted for.

  Commit: 565a9ac7df3815ed038938942be4cf1471de4755
      https://github.com/llvm/llvm-project/commit/565a9ac7df3815ed038938942be4cf1471de4755
  Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

  Log Message:
  -----------
  [SPIR-V] Disable Machine Sink pass in SPIR-V Backend (#116060)

Some standard passes that optimize machine instructions in SSA form uses
MI.isPHI() that doesn't account for OpPhi in SPIR-V and so are able to
break the CFG. MachineSink is among such passes (see for example
https://github.com/llvm/llvm-project/blob/1884ffc41c20b1e08b30eef4e8ebbcc54543a139/llvm/lib/CodeGen/MachineSink.cpp#L630),
so this PR disables the pass to ensure correctness of the generated
code.

There is a reproducer of the issue that demonstrates how MachineSink is
able to generate an invalid code for the SPIR-V Backend

```
error: line 6837: OpPhi must appear within a non-entry block before all non-OpPhi instructions (except for OpLine, which can be mixed with OpPhi).
  %z_fra_3_1 = OpPhi %uint %and187 %4250 %inc194 %4257 %uint_0 %4264
```

The reproducer is a part of SYCL end-to-end test suite
(https://github.com/intel/llvm/blob/sycl/sycl/test-e2e/DeviceLib/imf_fp32_rounding_test.cpp).
At the moment it doesn't seem feasible to make it a part of the SPIR-V
Backend test suite due to a far too big size of the intermediate LLVM IR
that causes the problem.

  Commit: 996553228f8b2f3219451a2514bd6f9380f13e28
      https://github.com/llvm/llvm-project/commit/996553228f8b2f3219451a2514bd6f9380f13e28
  Author: Maksim Panchenko <maks at fb.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M bolt/include/bolt/Core/BinarySection.h
    M bolt/lib/Core/BinarySection.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    A bolt/test/eh-frame-overwrite.test

  Log Message:
  -----------
  [BOLT] Overwrite .eh_frame and .gcc_except_table (#116755)

Under --use-old-text or --strict, we completely rewrite contents of EH
frames and exception tables sections. If new contents of either section
do not exceed the size of the original section, rewrite the section
in-place.

  Commit: 5681f756c058204d7e41d065f91c5f3c36a434a7
      https://github.com/llvm/llvm-project/commit/5681f756c058204d7e41d065f91c5f3c36a434a7
  Author: Adrian Prantl <aprantl at apple.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M lldb/docs/use/links.rst

  Log Message:
  -----------
  Fix broken link

  Commit: 5b79152937722a5b80c92146b7c2453401739d5f
      https://github.com/llvm/llvm-project/commit/5b79152937722a5b80c92146b7c2453401739d5f
  Author: David Green <david.green at arm.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M llvm/test/CodeGen/AArch64/phi.ll

  Log Message:
  -----------
  [AArch64] Make sure there is test coverage for ptr phis. NFC

  Commit: 174899f738b31216750ac59562475966b0b0be42
      https://github.com/llvm/llvm-project/commit/174899f738b31216750ac59562475966b0b0be42
  Author: Adrian Prantl <aprantl at apple.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M lldb/source/Utility/DiagnosticsRendering.cpp

  Log Message:
  -----------
  [lldb] Refactor helper by using iterators and in-place edits (NFC) (#116876)

Based on post-commit review feedback by Felipe Piovezan!

  Commit: df13acf344a4233777789d0052b3d09bec6a5180
      https://github.com/llvm/llvm-project/commit/df13acf344a4233777789d0052b3d09bec6a5180
  Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M clang/lib/CodeGen/CodeGenFunction.cpp
    M clang/lib/Sema/SemaDeclAttr.cpp
    A clang/test/CodeGenCUDASPIRV/spirv-attrs.cu
    A clang/test/SemaCUDA/spirv-attrs.cu

  Log Message:
  -----------
  [CudaSPIRV] Add support for optional spir-v attributes (#116589)

Add support for optional spir-v attributes.

Test plan:
ninja check-all

  Commit: 27046bad9751e85ba79db9248ff1f36e9d4d19eb
      https://github.com/llvm/llvm-project/commit/27046bad9751e85ba79db9248ff1f36e9d4d19eb
  Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
    M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp

  Log Message:
  -----------
  [mlir][XeGPU] Add a builder for xegpu.create_nd_tdesc op. (#116472)

The builder is needed to support dynamic meref as source operand in
xegpu.create_nd_tdesc op.

  Commit: 47ef5c4b7f85bc1c8a859d721db9fd1dde7b8d8e
      https://github.com/llvm/llvm-project/commit/47ef5c4b7f85bc1c8a859d721db9fd1dde7b8d8e
  Author: annuasd <97934297+annuasd at users.noreply.github.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M mlir/lib/Bindings/Python/DialectQuant.cpp
    M mlir/python/mlir/_mlir_libs/_mlir/dialects/quant.pyi
    M mlir/test/python/dialects/quant.py

  Log Message:
  -----------
  [mlir][Bindings] Fix missing return value of functions and incorrect type hint in pyi. (#116731)

The zero points of UniformQuantizedPerAxisType should be List[int].
And there are two methods missing return value.

Co-authored-by: 牛奕博 <niuyibo at niuyibodeMacBook-Pro.local>

  Commit: fc5c15b467dc30bf3c8a360635d78b7a49641904
      https://github.com/llvm/llvm-project/commit/fc5c15b467dc30bf3c8a360635d78b7a49641904
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M bolt/include/bolt/Core/BinarySection.h
    M bolt/lib/Core/BinarySection.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    A bolt/test/eh-frame-overwrite.test
    M clang/lib/CodeGen/CodeGenFunction.cpp
    M clang/lib/Sema/SemaDeclAttr.cpp
    A clang/test/CodeGenCUDASPIRV/spirv-attrs.cu
    A clang/test/SemaCUDA/spirv-attrs.cu
    M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
    M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
    M lldb/docs/use/links.rst
    M lldb/source/Utility/DiagnosticsRendering.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/CodeGen/AArch64/phi.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
    M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
    M mlir/lib/Bindings/Python/DialectQuant.cpp
    M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
    M mlir/python/mlir/_mlir_libs/_mlir/dialects/quant.pyi
    M mlir/test/python/dialects/quant.py

  Log Message:
  -----------
  Fix formatting

Created using spr 1.3.5

Compare: https://github.com/llvm/llvm-project/compare/75a6cd459d9b...fc5c15b467dc

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