[all-commits] [llvm/llvm-project] eff60d: [RISCV][GISel] Make extended loads and truncating ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eff60d83b0533954eda153fbbabb3e99d46bde94
      https://github.com/llvm/llvm-project/commit/eff60d83b0533954eda153fbbabb3e99d46bde94
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

This addresses some failures I've seen in testing on real code.



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