[all-commits] [llvm/llvm-project] e7fd10: [𝘀𝗽𝗿] changes introduced through rebase

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/main.riscv-support-__builtin_cpu_is
  Home:   https://github.com/llvm/llvm-project
  Commit: e7fd10eca321a59885e780cd51b5b533d4cc5940
      https://github.com/llvm/llvm-project/commit/e7fd10eca321a59885e780cd51b5b533d4cc5940
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-11-15 (Fri, 15 Nov 2024)

  Changed paths:
    R .icslock
    M bolt/unittests/Core/MCPlusBuilder.cpp
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/Basic/Attr.td
    M clang/include/clang/Basic/AttrDocs.td
    M clang/include/clang/Basic/BuiltinsX86.def
    M clang/include/clang/Basic/BuiltinsX86_64.def
    M clang/include/clang/Basic/TargetInfo.h
    M clang/include/clang/Basic/arm_sve.td
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/lib/Basic/Targets/AArch64.h
    M clang/lib/Driver/ToolChains/PS4CPU.cpp
    M clang/lib/Headers/CMakeLists.txt
    M clang/lib/Headers/immintrin.h
    R clang/lib/Headers/movrsintrin.h
    M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
    M clang/test/Analysis/ctor-trivial-copy.cpp
    M clang/test/CodeGen/AArch64/fmv-dependencies.c
    M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesd.c
    M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aese.c
    M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesimc.c
    M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesmc.c
    M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullb_128.c
    M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullt_128.c
    R clang/test/CodeGen/X86/movrs-builtins.c
    M clang/test/CodeGen/attr-ifunc.c
    R clang/test/CodeGen/ifunc-win.c
    M clang/test/CodeGen/ifunc.c
    M clang/test/Driver/aarch64-implied-sme-features.c
    M clang/test/Driver/aarch64-implied-sve-features.c
    M clang/test/Driver/print-supported-extensions-aarch64.c
    M clang/test/Driver/ps5-linker.c
    M clang/test/Preprocessor/aarch64-target-features.c
    M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
    M libcxx/CMakeLists.txt
    M libcxx/include/__memory/uninitialized_algorithms.h
    M libcxx/include/forward_list
    M libcxx/include/list
    M libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.pass.cpp
    M libcxx/utils/libcxx/test/format.py
    M lldb/test/Shell/Minidump/Windows/find-module.test
    M llvm/include/llvm/ADT/iterator_range.h
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/include/llvm/Support/YAMLTraits.h
    M llvm/include/llvm/TargetParser/RISCVTargetParser.h
    M llvm/lib/Analysis/InstructionSimplify.cpp
    M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
    M llvm/lib/Target/X86/X86InstrMisc.td
    M llvm/lib/TargetParser/AArch64TargetParser.cpp
    M llvm/lib/TargetParser/RISCVTargetParser.cpp
    M llvm/lib/Transforms/Utils/CodeExtractor.cpp
    M llvm/test/CodeGen/AArch64/ls64-inline-asm.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
    R llvm/test/CodeGen/X86/movrs-builtins.ll
    R llvm/test/CodeGen/X86/movrs-prefetch-builtins.ll
    M llvm/test/CodeGen/X86/no-non-zero-debug-loc-prologue.ll
    M llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll
    R llvm/test/DebugInfo/MIR/X86/dbg-prologue-backup-loc2.mir
    M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
    R llvm/test/DebugInfo/X86/dbg-prolog-end-backup-loc.ll
    M llvm/test/DebugInfo/X86/dbg-prolog-end.ll
    M llvm/test/DebugInfo/X86/empty-line-info.ll
    M llvm/test/DebugInfo/X86/loop-align-debug.ll
    M llvm/test/MC/AArch64/SVE2/aesd.s
    M llvm/test/MC/AArch64/SVE2/aese.s
    M llvm/test/MC/AArch64/SVE2/aesimc.s
    M llvm/test/MC/AArch64/SVE2/aesmc.s
    M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu.s
    M llvm/test/MC/AArch64/SVE2/pmullb-128.s
    M llvm/test/MC/AArch64/SVE2/pmullt-128.s
    R llvm/test/MC/Disassembler/X86/movrs.txt
    R llvm/test/MC/Disassembler/X86/prefetchrst2-32.txt
    R llvm/test/MC/Disassembler/X86/prefetchrst2-64.txt
    R llvm/test/MC/X86/movrs-att-64.s
    R llvm/test/MC/X86/movrs-intel-64.s
    R llvm/test/MC/X86/prefetchrst2-att-32.s
    R llvm/test/MC/X86/prefetchrst2-att-64.s
    R llvm/test/MC/X86/prefetchrst2-intel-32.s
    R llvm/test/MC/X86/prefetchrst2-intel-64.s
    M llvm/test/TableGen/riscv-target-def.td
    M llvm/test/Transforms/InstSimplify/cmp-alloca-offsets.ll
    M llvm/unittests/Support/YAMLIOTest.cpp
    M llvm/unittests/TargetParser/TargetParserTest.cpp
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
    M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
    M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
    R mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]



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