[all-commits] [llvm/llvm-project] c50bb9: [RISCV] Allow vslidedown.vx in isExtractSubvectorC...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c50bb99d87f845262d7fcf3a2ee50c087ac05181
      https://github.com/llvm/llvm-project/commit/c50bb99d87f845262d7fcf3a2ee50c087ac05181
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll

  Log Message:
  -----------
  [RISCV] Allow vslidedown.vx in isExtractSubvectorCheap for half VT case (#114886)

We have a special case where we allow the extract of the high half of a
vector and consider it cheap. However, we had previously required that
the type have no more than 32 elements for this to work. (Because
64/2=32, and the largest immediate for a vslidedown.vi is 31.)

This has the effect of pessimizing shuffle vector lowering for long
vectors - i.e. at SEW=e8, zvl128b, an m2 or m4 deinterleave can't be
matched because it gets scalarized during DAG construction and can't be
"profitably" rebuilt by DAG combine. Note that for RISCV, scalarization
via insert and extract is extremely expensive (i.e. two vslides per
element), so a slide + two half width shuffles is almost always a net
win. (i.e, this isn't really specific to vnsrl)

Separately, I want to look at the decision to scalarize at all, but it
seems worthwhile adjusting this while we're at it regardless.



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