[all-commits] [llvm/llvm-project] 8cb11b: Baseline Tablegen patch, with test, no tablegen ch...

[Sander de Smalen via All-commits]

  Branch: refs/heads/users/sdesmalen-arm/srlt-fix-tablegen-artificial-concat
  Home:   https://github.com/llvm/llvm-project
  Commit: 8cb11b0635d93082c7f210aa91fbf450c6c6a3bf
      https://github.com/llvm/llvm-project/commit/8cb11b0635d93082c7f210aa91fbf450c6c6a3bf
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    A llvm/test/TableGen/ArtificialSubregs.td

  Log Message:
  -----------
  Baseline Tablegen patch, with test, no tablegen changes


  Commit: 3cfdc3f809c5330d807027de2b0e6ab971afe385
      https://github.com/llvm/llvm-project/commit/3cfdc3f809c5330d807027de2b0e6ab971afe385
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    M llvm/test/TableGen/ArtificialSubregs.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen] Fix concatenation of subreg and artificial subregs

When CoveredBySubRegs is true and a sub-register consists of two
parts; a regular subreg and an artificial subreg, then TableGen
should consider both as a concatenation of subregs.

This happens for example when a 64-bit register 'D0' consists of
32-bit 'S0_HI' (artificial) and 'S0', and 'S0' consists of (16-bit)
'H0_HI' (artificial) and 'H0'. Then the concatenation should be:
S0_HI, H0_HI, H0.


Compare: https://github.com/llvm/llvm-project/compare/8cb11b0635d9%5E...3cfdc3f809c5

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