[all-commits] [llvm/llvm-project] c3724b: [RISCV] Add OperandType for vector rounding mode o...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c3724ba8667c695f29d5af93f2b0d1b23c1b41e7
      https://github.com/llvm/llvm-project/commit/c3724ba8667c695f29d5af93f2b0d1b23c1b41e7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-10-30 (Wed, 30 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll

  Log Message:
  -----------
  [RISCV] Add OperandType for vector rounding mode operands. (#114179)

Use TSFlags to distinquish which type of rounding mode it is. We use the same tablegen base classes for vxrm and frm sometimes so its hard to have different types for different instructions.



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