[all-commits] [llvm/llvm-project] ab5d3c: [RISCV] Assign different scheduling classes for VM...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ab5d3c9d359d84e454d54e8d91b5c834c42c5a47
      https://github.com/llvm/llvm-project/commit/ab5d3c9d359d84e454d54e8d91b5c834c42c5a47
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-10-28 (Mon, 28 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)

Split the scheduling classes of VMADC/VMSBC away from that of VADC/VSBC.
Because the former are technically mask-producing instructions rather
than normal vector arithmetics, which might have different performance
characteristics on some processors.

This is effectively NFC.



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