[all-commits] [llvm/llvm-project] 503d3d: [RISCV][CFI] add function epilogue cfi information

Fri Oct 4 02:26:00 PDT 2024

  Branch: refs/heads/users/dlav-sc/riscv-cfi-epilog
  Home:   https://github.com/llvm/llvm-project
  Commit: 503d3d80b6a8f2eba09ba29f4c2258946caf8485
      https://github.com/llvm/llvm-project/commit/503d3d80b6a8f2eba09ba29f4c2258946caf8485
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVFrameLowering.h

  Log Message:
  -----------
  [RISCV][CFI] add function epilogue cfi information

This patch adds CFI instructions in a function epilogue, that allows
lldb to obtain a valid backtrace at the end of functions.

  Commit: 22d7692a75c5f73e8ec491abcfbb20e0ffd46acf
      https://github.com/llvm/llvm-project/commit/22d7692a75c5f73e8ec491abcfbb20e0ffd46acf
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
    M llvm/test/CodeGen/RISCV/addrspacecast.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
    M llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/double-round-conv.ll
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
    M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/float-round-conv.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/frame-info.ll
    M llvm/test/CodeGen/RISCV/half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/kcfi-mir.ll
    M llvm/test/CodeGen/RISCV/large-stack.ll
    M llvm/test/CodeGen/RISCV/live-sp.mir
    M llvm/test/CodeGen/RISCV/llvm.exp10.ll
    M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
    M llvm/test/CodeGen/RISCV/lpad.ll
    M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
    M llvm/test/CodeGen/RISCV/nontemporal.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/pr58025.ll
    M llvm/test/CodeGen/RISCV/pr58286.ll
    M llvm/test/CodeGen/RISCV/pr63365.ll
    M llvm/test/CodeGen/RISCV/pr69586.ll
    M llvm/test/CodeGen/RISCV/pr88365.ll
    M llvm/test/CodeGen/RISCV/prolog-epilogue.ll
    M llvm/test/CodeGen/RISCV/push-pop-opt-crash.ll
    M llvm/test/CodeGen/RISCV/push-pop-popret.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
    M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
    M llvm/test/CodeGen/RISCV/rvv-cfi-info.ll
    M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
    M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
    M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
    M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
    M llvm/test/CodeGen/RISCV/rvv/localvar.ll
    M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
    M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
    M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
    M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
    M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
    M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
    M llvm/test/CodeGen/RISCV/rvv/remat.ll
    M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/stack-folding.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll
    M llvm/test/CodeGen/RISCV/shl-cttz.ll
    M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
    M llvm/test/CodeGen/RISCV/stack-inst-compress.mir
    M llvm/test/CodeGen/RISCV/stack-offset.ll
    M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/vlenb.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll
    M llvm/test/CodeGen/RISCV/xcvbi.ll
    M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
    M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
    M llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
    M llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
    M llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
    M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
    M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
    M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll

  Log Message:
  -----------
  [RISCV] update tests

  Commit: 524fe21184c08d9453c68a317beca4d0a934a1ae
      https://github.com/llvm/llvm-project/commit/524fe21184c08d9453c68a317beca4d0a934a1ae
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

  Log Message:
  -----------
  [RISCV][CFI] enable CFIFixup pass in RISCVTargetMachine

  Commit: eaea345c45528e46e0265c340b66c8c9fdc01e28
      https://github.com/llvm/llvm-project/commit/eaea345c45528e46e0265c340b66c8c9fdc01e28
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
    M llvm/test/CodeGen/RISCV/lpad.ll
    M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll

  Log Message:
  -----------
  [RISCV][CFI] CFIFixup update tests

  Commit: d6346e9824909b2f0c0e17bf49b6362c1c60264b
      https://github.com/llvm/llvm-project/commit/d6346e9824909b2f0c0e17bf49b6362c1c60264b
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/frame-info.ll

  Log Message:
  -----------
  [RISCV][CFI] add branch_and_tail_call test for CFIFixup

  Commit: 07ae4bcf38c49a0cdb13e61e4445f28a5ecd21c5
      https://github.com/llvm/llvm-project/commit/07ae4bcf38c49a0cdb13e61e4445f28a5ecd21c5
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

  Log Message:
  -----------
  [RISCV][CFI] fix __riscv_restore

  Commit: 2d7be29ce4600a34f575a750e435317f676d9503
      https://github.com/llvm/llvm-project/commit/2d7be29ce4600a34f575a750e435317f676d9503
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
    M llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
    M llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir

  Log Message:
  -----------
  [RISCV][CFI] __riscv_restore update tests

Compare: https://github.com/llvm/llvm-project/compare/8c86fc2e3d40...2d7be29ce460

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