[all-commits] [llvm/llvm-project] 9cf8c0: [RISCV][DAGCombine] Combine `sext_inreg (shl X, Y)...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9cf8c094c77db1ed9e63322bedcf28b76e5c5a43
      https://github.com/llvm/llvm-project/commit/9cf8c094c77db1ed9e63322bedcf28b76e5c5a43
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-10-04 (Fri, 04 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64zbs.ll

  Log Message:
  -----------
  [RISCV][DAGCombine] Combine `sext_inreg (shl X, Y), i32` into `sllw X, Y` (#111101)

Alive2: https://alive2.llvm.org/ce/z/ncf36D



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