[all-commits] [llvm/llvm-project] 9fd752: [LLVM] Port SVE tests in llvm/test/CodeGen/AArch64...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9fd75233ca757cf172d10703ac82fc162ef8ec0e
      https://github.com/llvm/llvm-project/commit/9fd75233ca757cf172d10703ac82fc162ef8ec0e
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2024-10-03 (Thu, 03 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/AArch64/DAGCombine_vscale.ll
    M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
    M llvm/test/CodeGen/AArch64/sme-disable-rematerialize-with-streaming-mode-changes.ll
    M llvm/test/CodeGen/AArch64/sve-adr.ll
    M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
    M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
    M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fadda-select.ll
    M llvm/test/CodeGen/AArch64/sve-fold-loadext-and-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll
    M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve-int-imm.ll
    M llvm/test/CodeGen/AArch64/sve-int-log-imm.ll
    M llvm/test/CodeGen/AArch64/sve-int-mulh-pred.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm-zero.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-undef.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-undef.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret-no-streaming.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-undef.ll
    M llvm/test/CodeGen/AArch64/sve-knownbits.ll
    M llvm/test/CodeGen/AArch64/sve-splat-one-and-ptrue.ll
    M llvm/test/CodeGen/AArch64/sve-splat-sext.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-stepvector.ll
    M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
    M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
    M llvm/test/CodeGen/AArch64/sve2-int-mul.ll
    M llvm/test/CodeGen/AArch64/sve2-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve2-sra.ll

  Log Message:
  -----------
  [LLVM] Port SVE tests in llvm/test/CodeGen/AArch64 to use splat()

This is preparation work towards making such splats use Constant{Int,FP}
by default for scalable vectors.



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