[all-commits] [llvm/llvm-project] 40b8a0: [RISCV][GISEL] Generate VLMax using -1 constant (#...
Michael Maitland via All-commits
all-commits at lists.llvm.org
Wed Oct 2 13:06:43 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 40b8a0fd174397e87925da3f1837d74d5d663a50
https://github.com/llvm/llvm-project/commit/40b8a0fd174397e87925da3f1837d74d5d663a50
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-10-02 (Wed, 02 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir
R llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr.mir
Log Message:
-----------
[RISCV][GISEL] Generate VLMax using -1 constant (#110778)
SelectionDAG uses ISD::REGISTER and uses RISCV::X0 to represent VLMAX.
Then in ComplexPattern VLOpt uses selectVLOp to convert RISCV::X0 to
RISCV::VLMaxSentinel.
The original legalization patch for G_SPLAT_VECTOR used Register
RISCV::X0 directly. $x0 has no LLT type, so GIComplexOperandMatcher has
no way of matching.
The approach we are changing to here will allow us to successfully use
GIComplexOperandMatcher to implement the ComplexMatcherFn selectVLOp in
GISEL since the operand now has a type.
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