[all-commits] [llvm/llvm-project] 836852: [RISCV][CFI] enable CFIFixup pass in RISCVTargetMa...

[dlav-sc via All-commits]

  Branch: refs/heads/users/dlav-sc/riscv-cfi-epilog
  Home:   https://github.com/llvm/llvm-project
  Commit: 836852dbcdfd4b864d5d667e238cdd0c87b64f49
      https://github.com/llvm/llvm-project/commit/836852dbcdfd4b864d5d667e238cdd0c87b64f49
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-02 (Wed, 02 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

  Log Message:
  -----------
  [RISCV][CFI] enable CFIFixup pass in RISCVTargetMachine


  Commit: 51751b59c2b96512ce152296d9e62af4d3345278
      https://github.com/llvm/llvm-project/commit/51751b59c2b96512ce152296d9e62af4d3345278
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-02 (Wed, 02 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
    M llvm/test/CodeGen/RISCV/lpad.ll
    M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll

  Log Message:
  -----------
  [RISCV][CFI] CFIFixup update tests


  Commit: 0573a78ba57d452b3f6a3f50f964a84fb9fb6ae5
      https://github.com/llvm/llvm-project/commit/0573a78ba57d452b3f6a3f50f964a84fb9fb6ae5
  Author: Daniil Avdeev <daniil.avdeev at syntacore.com>
  Date:   2024-10-02 (Wed, 02 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/frame-info.ll

  Log Message:
  -----------
  [RISCV][CFI] add branch_and_tail_call test for CFIFixup


Compare: https://github.com/llvm/llvm-project/compare/8bb14c199c2c...0573a78ba57d

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