[all-commits] [llvm/llvm-project] bc91f3: [RISCV] Add 32 bit GPR sub-register for Zfinx. (#1...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bc91f3cdd57cbe4b0a456626f52960158cb3232f
      https://github.com/llvm/llvm-project/commit/bc91f3cdd57cbe4b0a456626f52960158cb3232f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-10-01 (Tue, 01 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
    M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/float-arith.ll
    M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-frem.ll
    M llvm/test/CodeGen/RISCV/float-imm.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/kcfi-mir.ll
    M llvm/test/CodeGen/RISCV/llvm.frexp.ll
    A llvm/test/CodeGen/RISCV/make-compressible-zfinx.mir

  Log Message:
  -----------
  [RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to only spill 32 bits.
    
I've added CodeGenOnly instructions for load/store using GPRF32 as that gave better results than insert_subreg/extract_subreg.
    
Function arguments use this new GPRF32 register class for f32 arguments with Zfinx. Eliminating the need to use RISCVISD::FMV* nodes.
    
This is similar to #107446 which adds a 16 bit register class.



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