[all-commits] [llvm/llvm-project] d7e0c0: [RISCV][GISEL] regbankselect for G_VMCLR_VL (#110746)

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d7e0c08ab9bfa73b27c734d37ca57780a3d397cb
      https://github.com/llvm/llvm-project/commit/d7e0c08ab9bfa73b27c734d37ca57780a3d397cb
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-10-01 (Tue, 01 Oct 2024)

  Changed paths:
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr.mir

  Log Message:
  -----------
  [RISCV][GISEL] regbankselect for G_VMCLR_VL (#110746)

These are genereated when legalizing G_SPLAT_VECTOR



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