[all-commits] [llvm/llvm-project] 3ba409: [AMDGPU] Check vector sizes for physical register ...

[Fabian Ritter via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ba4092c066b589d6c16fcca2f2826cd6f51140f
      https://github.com/llvm/llvm-project/commit/3ba4092c066b589d6c16fcca2f2826cd6f51140f
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2024-10-01 (Tue, 01 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
    A llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
    A llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size.ll

  Log Message:
  -----------
  [AMDGPU] Check vector sizes for physical register constraints in inline asm (#109955)

For register constraints that require specific register ranges, the
width of the range should match the type of the associated
parameter/return value. With this PR, we error out when that is not the
case. Previously, these cases would hit assertions or llvm_unreachables.

The handling of register constraints that require only a single register
remains more lenient to allow narrower non-vector types for the
associated IR values. For example, constraining an i16 or i8 value to a
32-bit register is still allowed.

Fixes #101190.

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>



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