[all-commits] [llvm/llvm-project] 23c085: [RISCV][VCIX] Add vcix_state to GNU inline assembl...

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 23c0850d2e860c5773da6e4ee4ecf9802ba62202
      https://github.com/llvm/llvm-project/commit/23c0850d2e860c5773da6e4ee4ecf9802ba62202
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2024-09-30 (Mon, 30 Sep 2024)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    A llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll

  Log Message:
  -----------
  [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)

https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/56
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications