[all-commits] [llvm/llvm-project] ac0f64: [AMDGPU] Split vgpr regalloc pipeline (#93526)

Mon Sep 30 07:26:03 PDT 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac0f64f06d67a93817ccd9a3c529ad40920115c9
      https://github.com/llvm/llvm-project/commit/ac0f64f06d67a93817ccd9a3c529ad40920115c9
  Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
  Date:   2024-09-30 (Mon, 30 Sep 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    A llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
    M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
    M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
    M llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
    M llvm/test/CodeGen/AMDGPU/frame-index.mir
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
    M llvm/test/CodeGen/AMDGPU/pr51516.mir
    M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
    M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/remat-vop.mir
    M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
    R llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
    M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
    M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
    M llvm/test/CodeGen/AMDGPU/spill192.mir
    M llvm/test/CodeGen/AMDGPU/spill224.mir
    M llvm/test/CodeGen/AMDGPU/spill288.mir
    M llvm/test/CodeGen/AMDGPU/spill320.mir
    M llvm/test/CodeGen/AMDGPU/spill352.mir
    M llvm/test/CodeGen/AMDGPU/spill384.mir
    M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
    M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
    M llvm/test/CodeGen/AMDGPU/trap-abis.ll
    M llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
    A llvm/test/CodeGen/AMDGPU/wwm-regalloc-error.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll

  Log Message:
  -----------
  [AMDGPU] Split vgpr regalloc pipeline (#93526)

Allocating wwm-registers and per-thread VGPR operands
together imposes many challenges in the way the
registers are reused during allocation. There are
times when regalloc reuses the registers of regular
VGPRs operations for wwm-operations in a small range
leading to unwantedly clobbering their inactive lanes
causing correctness issues that are hard to trace.

This patch splits the VGPR allocation pipeline further
to allocate wwm-registers first and the regular VGPR
operands in a separate pipeline. The splitting would
ensure that the physical registers used for wwm
allocations won't take part in the next allocation
pipeline to avoid any such clobbering.

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