[all-commits] [llvm/llvm-project] 78ff73: [ARM] Fix VMOVRRD combine with non-canonical inser...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78ff736db2313642c3d8dd74beee3bc0b21c5c2a
      https://github.com/llvm/llvm-project/commit/78ff736db2313642c3d8dd74beee3bc0b21c5c2a
  Author: David Green <david.green at arm.com>
  Date:   2024-09-24 (Tue, 24 Sep 2024)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll

  Log Message:
  -----------
  [ARM] Fix VMOVRRD combine with non-canonical inserts. (#109639)

In some situations, in the test case here with the multiple calls being
late legalized, we can see inserts of the form:
```
     b = insert a, x, 0
    c = insert b, y, 1
   d = insert c, z, 0
  bc = bitcast d
 e = extract bc, 0
r = vmovrrd e
```
The redundant insert will usually be removed, but in some cases are not
prior to PerformVMOVRRDCombine. The code was finding the first insert
from each lane (x and y), as opposed to the last (z and y).



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