[all-commits] [llvm/llvm-project] f6a8eb: [AMDGPU][MC] Disallow null as saddr in flat instru...

[Jun Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6a8eb98b13ee50c67ecf4804461a23fba7398aa
      https://github.com/llvm/llvm-project/commit/f6a8eb98b13ee50c67ecf4804461a23fba7398aa
  Author: Jun Wang <jwang86 at yahoo.com>
  Date:   2024-09-24 (Tue, 24 Sep 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
    M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
    M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/MC/AMDGPU/flat-global.s
    A llvm/test/MC/AMDGPU/gfx10_flat_instructions_err.s
    A llvm/test/MC/AMDGPU/gfx11_flat_instructions_err.s
    A llvm/test/MC/AMDGPU/gfx12_flat_instructions_err.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt

  Log Message:
  -----------
  [AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)

Some flat instructions have an saddr operand. When 'null' is provided as
saddr, it may have the same encoding as another instruction. For
example, the instructions 'global_atomic_add v1, v2, null' and
'global_atomic_add v[1:2], v2, off' have the same encoding. This patch
disallows having null as saddr.



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