[all-commits] [llvm/llvm-project] 93baa0: [LegalizeVectorTypes] Preserve original MemoryOper...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 93baa018e09bb3d4d5f4da0232321aff204caaeb
      https://github.com/llvm/llvm-project/commit/93baa018e09bb3d4d5f4da0232321aff204caaeb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-23 (Mon, 23 Sep 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

  Log Message:
  -----------
  [LegalizeVectorTypes] Preserve original MemoryOperand and MemVT when widening fixed vector load to vp_load. (#109473)

Previously we were building a new memoperand with the size of the widened VT. This was causing a failure in our downstream with non-power of 2 vectorization. Alias analysis allowed rescheduling a 3 element vector load past 2 out of 3 scalar stores that overwrite what it was supposed to read.

Alias analysis considers it undefined behavior to read more than the size of the underlying object. There is an exception if the underying objects is sufficiently aligned, but that doesn't apply in my failing case.



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