[all-commits] [llvm/llvm-project] de6d7a: [RISCV] Expand Zfa fli+fneg cases during lowering ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: de6d7a6c3093f725bec6980e925166f0f363687a
      https://github.com/llvm/llvm-project/commit/de6d7a6c3093f725bec6980e925166f0f363687a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-11 (Wed, 11 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    M llvm/test/CodeGen/RISCV/double-zfa.ll
    M llvm/test/CodeGen/RISCV/float-zfa.ll
    M llvm/test/CodeGen/RISCV/half-zfa.ll

  Log Message:
  -----------
  [RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316)

Most of the constants fli can generate are positive numbers. We can use
fli+fneg to generate their negative versions.

Previously, we considered such negative constants as "legal" and let
isel generate the fli+fneg. However, it is useful to expose the fneg to
DAG combines to fold with fadd to produce fsub or with fma to produce
fnmadd, fnmsub, or fmsub.

This patch moves the fneg creation to lowering so that the fneg will be
visible to the last DAG combine.

I might move the rest of Zfa handling from isel to lowering as a follow
up.

Fixes #107772.



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