[all-commits] [llvm/llvm-project] 41402c: [RISCV][GISel] Use CCValAssign::getCustomReg for c...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41402c6a8aa3a4336122bdb4530fb05538efedba
      https://github.com/llvm/llvm-project/commit/41402c6a8aa3a4336122bdb4530fb05538efedba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-03 (Tue, 03 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll

  Log Message:
  -----------
  [RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<->GPR. (#105700)

This gives us much better control of the generated code for GISel. I've
tried to closely match the current gisel code, but it looks like we had
2 layers of G_ANYEXT in some cases before.

SelectionDAG now checks needsCustom() instead of detecting the special
cases in the Bitcast handler.

Unfortunately, IRTranslator for bitcast still generates copies between
register classes of different sizes. Because of this we can't handle
i16<->f16 bitcasts without crashing. Not sure if I should teach
RISCVInstrInfo::copyPhysReg to allow copies between FPR16 and GPR or if
I should convert the copies to instructions in GISel.



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