[all-commits] [llvm/llvm-project] 3e7984: [LegalizeDAG][RISCV] Don't promote f16 vector ISD:...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e798476de466e8a051d3e753db379731a8d9705
      https://github.com/llvm/llvm-project/commit/3e798476de466e8a051d3e753db379731a8d9705
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-03 (Tue, 03 Sep 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll

  Log Message:
  -----------
  [LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (#106652)

The fp_extend will canonicalize NaNs which is not the semantics of
FNEG/FABS/FCOPYSIGN.

For fixed vectors I'm scalarizing due to test changes on other targets
where the scalarization is expected. I will try to address in a follow
up.

For scalable vectors, we bitcast to integer and use integer logic ops.



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