[all-commits] [llvm/llvm-project] 922558: [RISCV] Remove registers from ins of Priv instruct...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 922558f47446fc732aa474f7bffc3190b4ffab43
      https://github.com/llvm/llvm-project/commit/922558f47446fc732aa474f7bffc3190b4ffab43
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-29 (Mon, 29 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  -----------
  [RISCV] Remove registers from ins of Priv instructions. (#100857)

The rd and rs1 encoding are already forced to 0s. We don't need
registers too.



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