[all-commits] [llvm/llvm-project] 7647f8: [RISCV] Add isel special case for (and (srl X, c2)...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7647f88234cadf0aed019abb1fc723c6708b871c
      https://github.com/llvm/llvm-project/commit/7647f88234cadf0aed019abb1fc723c6708b871c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-29 (Mon, 29 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add isel special case for (and (srl X, c2), c1) -> (slli_uw (srli x, c2+c3), c3). (#100966)

Where c1 is a shifted mask with 32 set bits and c3 trailing zeros.

Fixes #100936.



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