[all-commits] [llvm/llvm-project] 9bd97f: [RISCV] Remove IsRV64 from XVentanaCondOps pattern...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9bd97fcf1385efea2dc130ee4fa78665fa6c9205
      https://github.com/llvm/llvm-project/commit/9bd97fcf1385efea2dc130ee4fa78665fa6c9205
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-27 (Sat, 27 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
    M llvm/test/CodeGen/RISCV/condops.ll

  Log Message:
  -----------
  [RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)

Ventana doesn't have RV32 cores so the instructions aren't really
supported for RV32, but there's nothing specifically 64-bit about them.

My goal here is to fix cannot select errors if XVentanaCondOps is
enabled on RV32. Alternatively, we could quality the lowering code to
also check IsRV64 so that we don't create RISCVISD::CZERO* nodes. Fixing
the isel patterns seemed simpler.

Fixes #100855.



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