[all-commits] [llvm/llvm-project] b91c75: [RISCV] Add unit strided load/store to whole regis...
darkbuck via All-commits
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Tue Jul 23 23:11:16 PDT 2024
Branch: refs/heads/users/darkbuck/spr/simplifycfg-skip-threading-if-the-target-may-have-divergent-branches
Home: https://github.com/llvm/llvm-project
Commit: b91c75fcaeea47d54ac5d15b45f079bf44681dc4
https://github.com/llvm/llvm-project/commit/b91c75fcaeea47d54ac5d15b45f079bf44681dc4
Author: Luke Lau <luke at igalia.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
Log Message:
-----------
[RISCV] Add unit strided load/store to whole register peephole (#100116)
This adds a new vector peephole that converts unmasked, VLMAX
vleN.v/vseN.v to their whole register equivalents.
It replaces the existing tablegen patterns on ISD::LOAD/ISD::STORE and
is a bit more general since it also catches VP loads and stores and
@llvm.riscv intrinsics.
The heavy lifting of detecting a VLMAX AVL and an all-ones mask is
already taken care of by existing peepholes.
Commit: 599f8e1120db8c8c7a5e42134ea52650e8fb0f1c
https://github.com/llvm/llvm-project/commit/599f8e1120db8c8c7a5e42134ea52650e8fb0f1c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
Reland "[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)"
This reverts commit f1905f064451bf688577976a13000c9c47e58452.
This relands commit 19cf8deabe1124831164987f1b9bf2f806c0a875.
There were issues with the preprocessor includes that should have
excluded MSVC still including clang functions building on windows and
using intrin.h. This relanding fixes this behavior by additionally
wrapping the uses of __get_cpuid and __get_cpuid_count in _MSC_VER so
that clang in MSVC mode, which includes intrin.h, does not have any
conflicts.
Commit: d27ee36cdef28845b4aba4f438c7d8bef4be4da7
https://github.com/llvm/llvm-project/commit/d27ee36cdef28845b4aba4f438c7d8bef4be4da7
Author: Kai Yan <aklkaiyan at tencent.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/WindowScheduler.cpp
A llvm/test/CodeGen/Hexagon/swp-ws-zero-cost.mir
Log Message:
-----------
[llvm][CodeGen] Fixed max cycle calculation with zero-cost instructions for window scheduler (#99454)
We discovered some scheduling failures occurring when zero-cost
instructions were involved. This issue will be addressed by this patch.
Commit: 2d6ff0c533aa1b0fe6d91764846f636c4a4e911c
https://github.com/llvm/llvm-project/commit/2d6ff0c533aa1b0fe6d91764846f636c4a4e911c
Author: Kai Yan <aklkaiyan at tencent.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir
Log Message:
-----------
[llvm][CodeGen] Added missing initialization failure information for window scheduler (#99449)
Added missing initialization failure information for window scheduler.
Commit: e386aacb747b4512dedf481ad83e054d3dd641e6
https://github.com/llvm/llvm-project/commit/e386aacb747b4512dedf481ad83e054d3dd641e6
Author: hev <wangrui at loongson.cn>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/test/CodeGen/LoongArch/rotl-rotr.ll
Log Message:
-----------
[LoongArch] Fix codegen for ISD::ROTR (#100292)
This patch fixes the code generation for IR:
sext i32 (trunc i64 (rotr i64 %x, i64 %y) to i32) to i64
Commit: 6810c05ccaeea318bc06076680a9a843b02a1881
https://github.com/llvm/llvm-project/commit/6810c05ccaeea318bc06076680a9a843b02a1881
Author: Luke Lau <luke at igalia.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/pr99782.ll
Log Message:
-----------
[RISCV] Update test for #99821 after #100116. NFC
Commit: cd1a2ede2f6a741adf34fc5b57eb73aa149b515c
https://github.com/llvm/llvm-project/commit/cd1a2ede2f6a741adf34fc5b57eb73aa149b515c
Author: Kai Yan <aklkaiyan at tencent.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/MachinePipeliner.cpp
A llvm/test/CodeGen/Hexagon/swp-ws-pragma-initiation-interval-fail.mir
Log Message:
-----------
[llvm][CodeGen] Added a new restriction for II by pragma in window scheduler (#99448)
Added a new restriction for window scheduling.
Window scheduling is disabled when llvm.loop.pipeline.initiationinterval
is set.
Commit: 2ca300f914b1bdeef5f08415bbcbf1803c186401
https://github.com/llvm/llvm-project/commit/2ca300f914b1bdeef5f08415bbcbf1803c186401
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CMakeLists.txt
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
A llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
Log Message:
-----------
[GlobalIsel][NFC] Move cast code (#100196)
Preparation for more cast combines
Commit: 6942f1d5aa232face8269ce78c4de7d45571a8e9
https://github.com/llvm/llvm-project/commit/6942f1d5aa232face8269ce78c4de7d45571a8e9
Author: Zhaoshi Zheng <zhaoshiz at quicinc.com>
Date: 2024-07-23 (Tue, 23 Jul 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
M mlir/test/Dialect/Linalg/vectorization-unsupported.mlir
A mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_1d.mlir
A mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_2d.mlir
Log Message:
-----------
[MLIR][Linalg] Scalable Vectorization of Reduction on the Trailing Dimension (#97788)
Allow scalable vectorization of linalg::reduce and linalg::generic that has
reduction iterator(s) with two restrictions:
1. The reduction dim is the last (innermost) dim of the op; and
2. Only the reduction dim is requested for scalable vectorization.
One exception is that scalable vectorization of the reduction dim in
Matmul-like ops are not supported even above restrictions are met.
Allowed combinations of scalable flags and iterator types:
Matmul:
Iterators: ["parallel", "parallel", "reduction"]
Scalable Flags: ["true", "true", "false"]
["false", "true", "false"]
Matvec:
Iterators: ["parallel", "reduction"]
Scalable Flags: ["false", "true"]
["true", "false"]
Commit: 6461e537815f7fa68cef06842505353cf5600e9c
https://github.com/llvm/llvm-project/commit/6461e537815f7fa68cef06842505353cf5600e9c
Author: Fangrui Song <i at maskray.me>
Date: 2024-07-23 (Tue, 23 Jul 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/warn-fsyntax-only.c
Log Message:
-----------
[Driver] Don't claim -c/-S
Remove the TODO I left in commit
a07b135ce0c0111bd83450b5dc29ef0381cdbc39.
We will now warn about `-c/-S` with `-fsyntax-only`. This relands #98607
with a specific target triple.
Commit: 2ae862b74b3b132b6682350d47a095e733c337ce
https://github.com/llvm/llvm-project/commit/2ae862b74b3b132b6682350d47a095e733c337ce
Author: Hongyu Chen <hongyc4 at uci.edu>
Date: 2024-07-23 (Tue, 23 Jul 2024)
Changed paths:
M lld/ELF/ScriptLexer.cpp
M lld/ELF/ScriptLexer.h
M lld/ELF/ScriptParser.cpp
Log Message:
-----------
[ELF] Remove `consumeLabel` in ScriptLexer (#99567)
This commit removes `consumeLabel` since we can just use consume
function to have the same functionalities.
Commit: 7b619730d9e2bcc2ab1588574ed94ae19c4b8654
https://github.com/llvm/llvm-project/commit/7b619730d9e2bcc2ab1588574ed94ae19c4b8654
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M clang/test/AST/Interp/literals.cpp
Log Message:
-----------
[clang][Interp][test] Try to make a test case work on Windows
Commit: 9d45b450f26a1ad669d4ceaac2c36aff4b80bfde
https://github.com/llvm/llvm-project/commit/9d45b450f26a1ad669d4ceaac2c36aff4b80bfde
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
A llvm/test/Transforms/InstCombine/remquo.ll
A llvm/test/Transforms/InstCombine/remquol-fp128.ll
A llvm/test/Transforms/InstCombine/remquol-fp80.ll
A llvm/test/Transforms/InstCombine/remquol-ppc-fp128.ll
Log Message:
-----------
[SimplifyLibCalls] Constant fold `remquo` (#99647)
This patch adds constant folding support for `remquo`.
Reference: https://en.cppreference.com/w/cpp/numeric/math/remquo
Closes https://github.com/llvm/llvm-project/issues/99497.
Commit: f4e8fbc5e90a4f2959a0eb6d7b01e7e279fb693b
https://github.com/llvm/llvm-project/commit/f4e8fbc5e90a4f2959a0eb6d7b01e7e279fb693b
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2024-07-23 (Tue, 23 Jul 2024)
Changed paths:
M compiler-rt/test/nsan/CMakeLists.txt
A compiler-rt/test/nsan/alloca.cpp
A compiler-rt/test/nsan/helpers.h
M compiler-rt/test/nsan/lit.cfg.py
M compiler-rt/test/nsan/lit.site.cfg.py.in
A compiler-rt/test/nsan/sum.cpp
Log Message:
-----------
[compiler-rt][nsan] Add lit config for tests (#100286)
Initial setup for tests.
Test plan: ninja check-nsan
Commit: 63ae1e955007287ecf048d706ce3e025d20f52b8
https://github.com/llvm/llvm-project/commit/63ae1e955007287ecf048d706ce3e025d20f52b8
Author: Luke Lau <luke at igalia.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
R llvm/test/CodeGen/RISCV/pr89833.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
R llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
Log Message:
-----------
[RISCV] Emit VP strided loads/stores in RISCVGatherScatterLowering (#98111)
RISCVGatherScatterLowering is the last user of
riscv_masked_strided_{load,store} after #98131 and #98112, this patch
changes it to emit the VP equivalent instead. This allows us to remove
the masked_strided intrinsics so we have only have one lowering path.
riscv_masked_strided_{load,store} didn't have AVL operands and were
always VLMAX, so this passes in the fixed or scalable element count to
the EVL instead, which RISCVVectorPeephole should now convert to VLMAX
after #97800.
For loads we also use a vp_select to get passthru (mask undisturbed)
behaviour
Commit: dbe308c000f3401cbf6bb55f2b8d606fe091dcfe
https://github.com/llvm/llvm-project/commit/dbe308c000f3401cbf6bb55f2b8d606fe091dcfe
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ExprConstant.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
M clang/test/SemaCXX/constant-expression-cxx2b.cpp
M clang/test/SemaCXX/cxx23-invalid-constexpr.cpp
Log Message:
-----------
[clang][ExprConst] Allow non-literal types in C++23 (#100062)
Instead of diagnosing non-literal types in C++23, allow them and later
diagnose them differently, e.g. because they have a non-constexpr
constructor, destructor, etc.
For this test:
```c++
struct NonLiteral {
NonLiteral() {}
};
constexpr int foo() {
NonLiteral L;
return 1;
}
// static_assert(foo() == 1);
```
The current diagnostics with c++20/c++23 are:
```console
~/code/llvm-project/build » clang -c array.cpp -std=c++20
array.cpp:91:14: error: variable of non-literal type 'NonLiteral' cannot be defined in a constexpr function before C++23
91 | NonLiteral L;
| ^
array.cpp:87:8: note: 'NonLiteral' is not literal because it is not an aggregate and has no constexpr constructors other than copy or move constructors
87 | struct NonLiteral {
| ^
1 error generated.
------------------------------------------------------------
~/code/llvm-project/build » clang -c array.cpp -std=c++23
(no output)
```
With the `static_assert` enabled, compiling with `-std=c++23` prints:
```console
array.cpp:95:15: error: static assertion expression is not an integral constant expression
95 | static_assert(foo() == 1);
| ^~~~~~~~~~
array.cpp:91:14: note: non-literal type 'NonLiteral' cannot be used in a constant expression
91 | NonLiteral L;
| ^
array.cpp:95:15: note: in call to 'foo()'
95 | static_assert(foo() == 1);
| ^~~~~
1 error generated.
```
As mentioned in #60311, this is confusing. The output with c++20
suggests that using c++23 will make the problem go away, but it's
diagnosed the same when running the function.
With this commit, the output instead diagnoses _why_ the non-literal
type can't be used:
```console
array.cpp:95:15: error: static assertion expression is not an integral constant expression
95 | static_assert(foo() == 1);
| ^~~~~~~~~~
array.cpp:91:14: note: non-constexpr constructor 'NonLiteral' cannot be used in a constant expression
91 | NonLiteral L;
| ^
array.cpp:95:15: note: in call to 'foo()'
95 | static_assert(foo() == 1);
| ^~~~~
array.cpp:88:3: note: declared here
88 | NonLiteral() {}
| ^
1 error generated.
```
Fixes #60311
Commit: 5540cc53ca4419729e449a1f19109598aab05de5
https://github.com/llvm/llvm-project/commit/5540cc53ca4419729e449a1f19109598aab05de5
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-07-24 (Wed, 24 Jul 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/AST/Interp/literals.cpp
M clang/test/CXX/drs/cwg18xx.cpp
A clang/test/Driver/warn-fsyntax-only.c
M clang/test/SemaCXX/constant-expression-cxx11.cpp
M clang/test/SemaCXX/constant-expression-cxx2b.cpp
M clang/test/SemaCXX/cxx23-invalid-constexpr.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/test/nsan/CMakeLists.txt
A compiler-rt/test/nsan/alloca.cpp
A compiler-rt/test/nsan/helpers.h
M compiler-rt/test/nsan/lit.cfg.py
M compiler-rt/test/nsan/lit.site.cfg.py.in
A compiler-rt/test/nsan/sum.cpp
M lld/ELF/ScriptLexer.cpp
M lld/ELF/ScriptLexer.h
M lld/ELF/ScriptParser.cpp
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/CodeGen/GlobalISel/CMakeLists.txt
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
A llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir
A llvm/test/CodeGen/Hexagon/swp-ws-pragma-initiation-interval-fail.mir
A llvm/test/CodeGen/Hexagon/swp-ws-zero-cost.mir
M llvm/test/CodeGen/LoongArch/rotl-rotr.ll
R llvm/test/CodeGen/RISCV/pr89833.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/pr99782.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
R llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
A llvm/test/Transforms/InstCombine/remquo.ll
A llvm/test/Transforms/InstCombine/remquol-fp128.ll
A llvm/test/Transforms/InstCombine/remquol-fp80.ll
A llvm/test/Transforms/InstCombine/remquol-ppc-fp128.ll
R llvm/test/Transforms/SimplifyCFG/AMDGPU/convergent.ll
A llvm/test/Transforms/SimplifyCFG/AMDGPU/skip-threading.ll
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
M mlir/test/Dialect/Linalg/vectorization-unsupported.mlir
A mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_1d.mlir
A mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_2d.mlir
Log Message:
-----------
rename test for a GPU target
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/3b376db8c6ae...5540cc53ca44
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