[all-commits] [llvm/llvm-project] b91c75: [RISCV] Add unit strided load/store to whole regis...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b91c75fcaeea47d54ac5d15b45f079bf44681dc4
      https://github.com/llvm/llvm-project/commit/b91c75fcaeea47d54ac5d15b45f079bf44681dc4
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-07-24 (Wed, 24 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll

  Log Message:
  -----------
  [RISCV] Add unit strided load/store to whole register peephole (#100116)

This adds a new vector peephole that converts unmasked, VLMAX
vleN.v/vseN.v to their whole register equivalents.

It replaces the existing tablegen patterns on ISD::LOAD/ISD::STORE and
is a bit more general since it also catches VP loads and stores and
@llvm.riscv intrinsics.

The heavy lifting of detecting a VLMAX AVL and an all-ones mask is
already taken care of by existing peepholes.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications