[all-commits] [llvm/llvm-project] e8e406: Fix sext_in_reg from i1 to i128

[Ulrich Weigand via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e8e406041e93e50d6f8259d2793dfbd08dd43b4a
      https://github.com/llvm/llvm-project/commit/e8e406041e93e50d6f8259d2793dfbd08dd43b4a
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2024-07-15 (Mon, 15 Jul 2024)

  Changed paths:
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    A llvm/test/CodeGen/SystemZ/vec-cmp-08.ll

  Log Message:
  -----------
  Fix sext_in_reg from i1 to i128

The combineSIGN_EXTEND_INREG routine was using
DAG.getConstant(-1, DL, VT), which does not result in
the expected value when VT has more than 64 bits.

Fix this by using DAG.getAllOnesConstant(DL, VT) instead.

Also add test cases for v1i128 comparisons (which triggers
the bug).



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