[all-commits] [llvm/llvm-project] 657dbc: [RISCV] Reorder shuffle operands if one side is an...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 657dbc3febb92d8e675b601d127b071c5ba61028
      https://github.com/llvm/llvm-project/commit/657dbc3febb92d8e675b601d127b071c5ba61028
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-07-11 (Thu, 11 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

  Log Message:
  -----------
  [RISCV] Reorder shuffle operands if one side is an identity (#98534)

Doing so allows one side to fold entirely into the mask applied to the
other recursive call (or a vmerge.vv at worst). This is a generalization
of the existing IsSelect case (both operands are selects), so I removed
that code in the process.

This actually started as an attempt to remove the IsSelect bit as I'd
thought it was fully redundant
with the recursive formulation, but digging into test deltas revealed
that we depended on that
to catch the majority of the identity cases, and that in turn we were
missing some cases where only RHS was an identity.



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