[all-commits] [llvm/llvm-project] d10063: [AArch64] Lower for power of 2 signed divides with...

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d1006315b5076e89c3a698e47761370d61b071e3
      https://github.com/llvm/llvm-project/commit/d1006315b5076e89c3a698e47761370d61b071e3
  Author: Allen <zhongyunde at huawei.com>
  Date:   2024-07-10 (Wed, 10 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sdivpow2.ll

  Log Message:
  -----------
  [AArch64] Lower for power of 2 signed divides with scalar type (#97879)

Expected same assemble for code which doesn't use sve registers when we
compile it with/without -msve-vector-bits=256.

Fix https://github.com/llvm/llvm-project/issues/97821



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