[all-commits] [llvm/llvm-project] 8b511e: [RISCV] Fix 0-offset aliases for compressed sp-bas...

[R via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8b511e14770781bd31b0c03bad790bdd82793dac
      https://github.com/llvm/llvm-project/commit/8b511e14770781bd31b0c03bad790bdd82793dac
  Author: R <rqou00 at gmail.com>
  Date:   2024-07-10 (Wed, 10 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/test/MC/RISCV/rv32fc-aliases-valid.s
    M llvm/test/MC/RISCV/rv64c-aliases-valid.s
    M llvm/test/MC/RISCV/rvc-aliases-valid.s
    M llvm/test/MC/RISCV/rvdc-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Fix 0-offset aliases for compressed sp-based opcodes (#98034)

The "26.3.1. Stack-Pointer-Based Loads and Stores" compressed opcodes
have access to all registers (except x0). Fix the opcode aliases with 0
offset so that the aliases also work for all registers, not only the RVC
registers.

Previously, LLVM would accept e.g. `c.lwsp x8, (sp)` but not e.g.
`c.lwsp x18, (sp)`, even though e.g. `c.lwsp x18, 0(sp)` would be
accepted.

This was noticed while implementing
https://github.com/llvm/llvm-project/pull/97925 . The implementation in
that other PR is indeed correct (i.e `qk.c.lhusp` et al are restricted
to the RVC registers).



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