[all-commits] [llvm/llvm-project] abde52: [CodeGen][NewPM] Port `LiveIntervals` to new pass ...

[paperchalice via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: abde52aa667118d18e9551ab87a15b95c267b3b6
      https://github.com/llvm/llvm-project/commit/abde52aa667118d18e9551ab87a15b95c267b3b6
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2024-07-10 (Wed, 10 Jul 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/LiveIntervals.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Passes/CodeGenPassBuilder.h
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/LiveDebugVariables.cpp
    M llvm/lib/CodeGen/LiveIntervals.cpp
    M llvm/lib/CodeGen/LiveRegMatrix.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/ModuloSchedule.cpp
    M llvm/lib/CodeGen/PHIElimination.cpp
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/RegAllocPBQP.cpp
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
    M llvm/lib/CodeGen/StackSlotColoring.cpp
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/lib/CodeGen/VirtRegMap.cpp
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
    M llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
    M llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
    M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
    M llvm/lib/Target/AMDGPU/GCNRegPressure.h
    M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
    M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
    M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
    M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
    M llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp
    M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
    M llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp
    M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
    M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
    M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
    M llvm/lib/Target/X86/X86TileConfig.cpp
    M llvm/test/CodeGen/AArch64/live-interval-analysis.mir
    M llvm/test/CodeGen/AMDGPU/liveness.mir
    M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
    M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
    M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
    M llvm/test/CodeGen/X86/invalid-liveness.mir
    M llvm/unittests/MI/LiveIntervalTest.cpp

  Log Message:
  -----------
  [CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.



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