[all-commits] [llvm/llvm-project] 8ab19d: [RISCV] Add -verify-machineinstrs to RISCVInsertVS...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ab19d2e7094c6816ea4f545eb24c503c79a9673
      https://github.com/llvm/llvm-project/commit/8ab19d2e7094c6816ea4f545eb24c503c79a9673
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-07-10 (Wed, 10 Jul 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

  Log Message:
  -----------
  [RISCV] Add -verify-machineinstrs to RISCVInsertVSETVLI MIR tests. NFC

Now that we're working with LiveIntervals, make sure that they're correct.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications