[all-commits] [llvm/llvm-project] 7e2f96: [MachineSink] Fix missing sinks along critical edg...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e2f96194fa56148281c0232b4fa0db5c9cabec3
      https://github.com/llvm/llvm-project/commit/7e2f96194fa56148281c0232b4fa0db5c9cabec3
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-07-09 (Tue, 09 Jul 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/test/CodeGen/AArch64/and-sink.ll
    M llvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
    M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll

  Log Message:
  -----------
  [MachineSink] Fix missing sinks along critical edges (#97618)

4e0bd3f improved early MachineLICM's capabilities to hoist COPY from
physical registers out of a loop. However, it accidentally broke one of
MachineSink's preconditions on sinking cheap instructions (in this case,
COPY) which considered those instructions being profitable to sink only
when there are at least two of them in the same def-use chain in the
same basic block. So if early MachineLICM hoisted one of them out,
MachineSink no longer sink rest of the cheap instructions. This results
in redundant load immediate instructions from the motivating example
we've seen on RISC-V.

This patch fixes this by teaching MachineSink that if there is more than
one demand to sink a register into the same block from different
critical edges, it should be considered profitable as it increases the
CSE opportunities.
This change also improves two of the AArch64's cases.



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