[all-commits] [llvm/llvm-project] ed5190: [RISCV] Emit VP strided load in mgather combine. N...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ed51908cec879c9dff435abdc70d8b03afc35c07
      https://github.com/llvm/llvm-project/commit/ed51908cec879c9dff435abdc70d8b03afc35c07
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-07-09 (Tue, 09 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Emit VP strided load in mgather combine. NFCI (#98112)

This combine is a duplication of the transform in
RISCVGatherScatterLowering but at the SelectionDAG level, so similarly
to #98111 we can replace the use of riscv_masked_strided_load with a VP
strided load.

Unlike #98111 we don't require #97800 or #97798 since it only operates
on fixed vectors with a non-zero stride.



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