[all-commits] [llvm/llvm-project] bb8998: [RISCV] Don't custom legalize vXf16 SPLAT_VECTOR w...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bb8998dd3b74a6936452d7ddeb341e79c1d8f001
      https://github.com/llvm/llvm-project/commit/bb8998dd3b74a6936452d7ddeb341e79c1d8f001
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-08 (Mon, 08 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

  Log Message:
  -----------
  [RISCV] Don't custom legalize vXf16 SPLAT_VECTOR with Zvfhmin without Zfhmin.

Marking SPLAT_VECTOR as Custom enables generic DAGCombine to turn
BUILD_VECTOR into SPLAT_VECTOR. We need to custom type legalize BUILD_VECTOR
without Zfhmin since we don't have the scalar f16 type. If we allow
SPLAT_VECTOR to be formed, we'll need to custom type legalize it too.

Easiest fix is to only enable SPLAT_VECTOR with Zvfhmin+Zfhmin. There's
still an issue that we need to properly support BUILD_VECTOR with Zvfhmin+Zfhmin.

Should fix the new case reported in #97849.

I've also changed the predicates to Zfhmin instead of ZfhminOrZhinxmin
since Zhinx isn't compatible with Zvfhmin.



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